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MPF5020CMBA0ES Datasheet(PDF) 39 Page - NXP Semiconductors |
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MPF5020CMBA0ES Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 106 page  NXP Semiconductors PF5020 Power management integrated circuit (PMIC) for high performance applications Symbol Parameter Min Typ Max Unit RESETBMCU_VOL RESETBMCU low output voltage −2.0 mA load current 0 — 0.4 V INTB_VOL INTB low output voltage −2.0 mA load current 0 — 0.4 V ENx_VIL ENx low input voltage — — 0.4 V ENx_VIH ENx high input voltage 1.4 — 5.5 V WDI_VIL WDI low input voltage — — 0.3*VDDIO V WDI_VIH WDI high input voltage 0.7*VDDIO — 5.5 V RWDI_PD WDI internal pull-down resistance 0.475 1.0 — MΩ PGOOD_VOL PGOOD low output voltage −2.0 mA load current 0 — 0.4 V PGOODx_VOL PGOODx low output voltage −2.0 mA load current 0 — 0.4 V TBBEN_VIL TBBEN low input voltage — — 0.4 V TBBEN_VIH TBBEN high input voltage 1.4 — 5.5 V RTBBEN_PD TBBEN internal pull-down resistance 0.475 1.0 — MΩ XFAILB_VIL XFAILB low input voltage — — 0.4 V XFAILB_VIH XFAILB high input voltage 1.4 — 5.5 V XFAILB_VOH XFAILB high output voltage Pulled-up to V1P5A V1P5A − 0.5 — — V XFAILB_VOL XFAILB low output voltage −2.0 mA load current 0 — 0.4 V SCL_VIL SCL low input voltage — — 0.3*VDDIO V SCL_VIH SCL high input voltage 0.7*VDDIO — VDDIO V SDA_VIL SDA low input voltage — — 0.3*VDDIO V SDA_VIH SDA high input voltage 0.7*VDDIO — VDDIO V SDA_VOL SDA low output voltage −20 mA load current 0 — 0.4 V Table 28. I/O electrical specifications...continued 14.9.1 PWRON PWRON is an input signal to the IC that acts as a power up event signal in the PF5020. The PWRON pin has two modes of operation as programed by the OTP_PWRON_MODE bit. When OTP_PWRON_MODE = 0, the PWRON pin operates in level sensitive mode. In this mode, the device is in the corresponding off mode when the PWRON pin is pulled low. Pulling the PWRON pin high is a necessary condition to generate a power on event. PWRON may be pulled up to VSNVS or VIN with an external 100 kΩ resistor if device is intended to come up automatically with VIN application. See Section 14.5 "Power up" for details on power up requirements. When OTP_PWRON_MODE = 1, the PWRON pin operates in edge sensitive mode. In this mode, PWRON is used as an input from a push button connected to the PMIC. When the switch is not pressed, the PWRON pin is pulled up to VIN externally through a 100 kΩ resistor. When the switch is pressed, the PWRON pin should be shorted to ground. The PWRON_S bit is low whenever the PWRON pin is at logic 0 and is high whenever the PWRON pin is at logic 1. The PWRON pin has a programmable debounce on the rising and falling edges as shown in Table 29. PF5020 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3.2 — 5 March 2024 39 / 106 |
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