TMD3721 datasheet(57/89 Pages) OSRAM

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[v3-00] 2023-May-26

TMD3721 − Register O ver view

PCFG4 Register (Address 0xDA)

Figure 76:

PCFG4 Register

CALIBSTAT Register (Address 0xDC)

Figure 77:

CALIBSTAT Register

Addr: 0xDA

PCFG4

Bit

Bit Name

Default

Access

Bit Description

7:1

Reserved

Reserved. Must be set to default value.

PROX_CAL_

VSYNC_EN

0RW

The bit enables proximity calibration synchronized to

the VSYNC signal with PSD delay. The proximity

calibration consists of 9 measurement cycles.

If the bit is set to 1, every cycle of the 9 measurement

cycles are synchronized to the VSYNC signal with PSD

delay.

If the bit is set to 0 and PVSYNC_EN is 1, only the first

measurement cycle is synchronized to the VSYNC

signal with PSD delay, the successive measurement

cycles run immediately after the first measurement

cycle.

If the bit is set to 0 and PVSYNC_EN is 0, all 9

measurement cycles of the proximity calibration run

immediately pulse burst irrespective of VSYNC signal.

Addr: 0xDC

CALIBSTAT

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

00000

Reserved. Must be set to default value.

OFFSET_

ADJUSTED

Bit is set when the proximity offset has been

automatically decremented if PROX_AUTO_

OFFSET_ADJ = 1 (see CALIBCFG register). This

bit can be cleared by writing 1 to it or setting

PROX_AUTO_OFFSET_ADJ to 0.

Reserved

Reserved. Must be set to default value.

CALIB_FINISHED

This flag indicates that calibration has

finished. This bit is a copy of the CINT bit in the

STATUS register. It will be cleared when the

CINT bit is cleared.

TMD3721 Datasheet(PDF) 57 Page - OSRAM GmbH

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