TMD3721 datasheet(33/89 Pages) OSRAM

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Datasheet, Public

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[v3-00] 2023-May-26

TMD3721 − Register O ver view

The frequency of consecutive proximity channel results outside

of threshold limits are counted; this count value is compared

against the PPERS value. If the counter is equal to the PPERS

value an interrupt is asserted. Any time a proximity channel

result is inside the threshold values the counter is cleared.

The frequency of consecutive ALS clear channel results outside

of threshold limits are counted; this count value is compared

against the APERS value. If the counter is equal to the APERS

setting an interrupt is asserted. Any time an ALS clear channel

result is inside the threshold values the counter is cleared.

CFG0 Register (Address 0x8D)

Figure 39:

CFG0 Register

Addr: 0x8D

CFG0

Bit

Bit Name

Default

Access

Bit Description

7ENAB_16_BIT_OP

Enables output of PDATA to be a 16-bit value when

APC is on. See PDATA (0xF4 and 0xF5) for details.

6:4

Reserved

001

Reserved. Must be set to default value.

3PWLONG

When PWLONG (PROX Wait Long) is asserted the wait

period as set by PWTIME is increased by a factor of 12

2AWLONG

When AWLONG (ALS Wait Long) is asserted the wait

period as set by AWTIME is increased by a factor of 12

1:0

Reserved

Reserved. Must be set to default value.

TMD3721 Datasheet(PDF) 33 Page - OSRAM GmbH