TMD3721 datasheet(73/89 Pages) OSRAM

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[v3-00] 2023-May-26

TMD3721 − Register O ver view

ALS data are stored in FIFO and read out from the register FIFO_

ADATA_7 to FIFO_ADATA_0. The data definition is based on the

configurations of TWO_CHANN_MODE and DOUBLE_DATA_

MODE as described in the following table. Depending on the

configurations, reading undefined registers returns zeros. The

data values will stay in registers until the FIFO_ADATA0 (0xFF)

is read. Whenever the FIFO_ADATA0 (0xFF) is read, the next set

of data is updated into all the ADATA registers. For the I²C block

read, when the address hits 0xFF, it wraps back according to the

configurations described in the Figure 106.

Figure 106:

FIFO ADATA Read Configuration

Name

TWO_CHAN_

MODE=0

DOUBLE_DATA_

MODE=0

TWO_CHAN_

MODE=0

DOUBLE_

DATA_MODE=1

TWO_CHAN_

MODE=1

DOUBLE_DATA_

MODE=0

TWO_CHAN_

MODE=1

DOUBLE_

DATA_MODE=1

FIFO_ADATA_7

BLUE data low byte

Undefined

FIFO_ADATA_6

BLUE data high byte

Undefined

FIFO_ADATA_5

GREEN data low byte

Undefined

FIFO_ADATA_4

GREEN data high

byte

Undefined

FIFO_ADATA_3

RED data low byte

BLUE data (8-bit)

CH1 (R+B) data low

byte

Undefined

FIFO_ADATA_2

RED data high byte

GREEN data (8-bit)

CH1 (R+B) data high

byte

Undefined

FIFO_ADATA_1

CLEAR data low byte

RED data (8-bit)

CH0 (C+G) data low

byte

CH1 (R+B) data

(8-bit)

FIFO_ADATA_0

CLEAR data high

byte

CLEAR data (8-bit)

CH0 (C+G) data high

byte

CH0 (C+G) data

(8-bit)

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