TMD3721 datasheet(47/89 Pages) OSRAM

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Page 46

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[v3-00] 2023-May-26

TMD3721 − Register O ver view

CFG3 Register (Address 0xAB)

Figure 60:

CFG3 Register

Addr: 0xAB

CFG3

Bit

Bit Name

Default

Access

Bit Description

7INT_READ_CLEAR

If set, the interrupt flag bits in the STATUS register

will be reset whenever the STATUS register is read

over I²C.

6:5

MODE_CFG

The register sets the operational mode of ALS and

Proximity measurement of the device.

Value

Operational Mode

Sequential Mode

Concurrent Mode

Full Parallel Mode

Unused Setting

4SAI

The Sleep After Interrupt bit is used to place the

device into a low power mode at the end of the

proximity /ALS cycle if an interrupt has been

generated. SAI doesn't modify any register bits

directly, it rather uses the interrupt signal to turn off

the oscillator. The device will appear as if PON=0,

however, PON will read as 1. The way to wake up the

device from SAI-sleep is by clearing the interrupts in

the status registers. Note that SAI is only available in

sequential mode.

PON

SAI

INT (low

active)

Oscillator

OFF

3PID_EN

When this bit is set, whenever a proximity pulse is

triggered during ASP1 ASP2 sampling period in Full

Parallel Mode, PID is written into the FIFO instead of

the actual ALS data.

Configure {PID_H, PID_L} for the PID value.

2:0

Reserved

001

Reserved. Must be set to default value.

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