TMD3721 datasheet(48/89 Pages) OSRAM

48 / 89 page

Datasheet, Public

Page 47

[v3-00] 2023-May-26

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TMD3721 − Register Overview

CFG6 Register (Address 0xAE)

Figure 61:

CFG6 Register

PWM_CFG Register (Address 0xB0)

Figure 62:

PWM_CFG Register

Addr: 0xAE

CFG6

Bit

Bit Name

Default

Access

Bit Description

Reserved

Reserved. Must be set to default value.

DISABLE_APC

Proximity automatic pulse control (APC) disable.

0 = APC enable

1 = APC disable

This bit should be set to 1 when calibration needs

to be performed

5:0

Reserved

111111

Reserved. Must be set to default value.

Addr: 0xB0

PWM_CFG

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

00000

Reserved. Must be set to default value.

2:1

PWM_CHG_DET_STP

PWM period change detection step.

Once PWM period changes from previous cycle by

step of period mentioned in the following table,

PWM_CHG_INT interrupt is generated if PWMIEN=1.

PWM_PRD={PWM_PRD_H, PWM_PRD_L}

Value

Timing

Compare with PWM_PRD[13:9]

Compare with PWM_PRD[13:8]

Compare with PWM_PRD[13:10]

Compare with PWM_PRD[13:11]

PWM_IN_EN

Enable XRES as a PWM input pin.

TMD3721 Datasheet(PDF) 48 Page - OSRAM GmbH

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