PIC18F6X2X datasheet(156/386 Pages) MICROCHIP

156 / 386 page

PIC18F6X2X/8X2X

DS39612A-page 154

Advance Information

 2003 Microchip Technology Inc.

16.3

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against either the TMR1 or TMR3

pin can be:

• driven high

• driven low

• toggled (high to low or low to high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (CCP4M3:CCP4M0). At the same time, the

interrupt flag bit CCP4IF is set.

16.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

16.3.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

16.3.3

SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCP4M3:CCP4M0 = 1010), the CCP4 pin is not

affected. Only a CCP interrupt is generated if enabled

and the CCP4IE bit is set.

16.3.4

SPECIAL EVENT TRIGGER

Although shown in Figure 16-3, the compare on match

special event triggers are not implemented on CCP4 or

CCP5; they are only available on ECCP1 and ECCP2.

Their operation is discussed in detail in Section 17.2.1.

FIGURE 16-3:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCP4CON register will force

the RG3/CCP4 compare output latch to

the default low level. This is not the

PORTG I/O data latch.

CCPR4H CCPR4L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP4IF

Match

RG3/CCP4 pin

TRISG<3>

CCP4CON<3:0>

Mode Select

Output Enable

TMR3H

TMR3L

T3CCP2

(ECCP1 and ECCP2 only)

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