PIC18F6X2X datasheet(155/386 Pages) MICROCHIP

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 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 153

PIC18F6X2X/8X2X

16.2

Capture Mode

In Capture mode, the CCPR4H:CCPR4L register pair

captures the 16-bit value of the TMR1 or TMR3 regis-

ters when an event occurs on pin RG3/CCP4. An event

is defined as one of the following:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge

The event is selected by the mode select bits,

CCP4M3:CCP4M0 (CCP4CON<3:0>). When a cap-

ture is made, the interrupt request flag bit CCP4IF

(PIR3<1>) is set; it must be cleared in software. If

another capture occurs before the value in register

CCPR4 is read, the old captured value is overwritten by

the new captured value.

16.2.1

CCP PIN CONFIGURATION

In Capture mode, the RG3/CCP4 pin should be

configured as an input by setting the TRISG<3> bit.

16.2.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode

or Synchronized Counter mode. In Asynchronous

Counter mode, the capture operation may not work.

The timer to be used with each CCP module is selected

in the T3CON register (see Section 16.1.1).

16.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP4IE (PIE3<1>) clear to avoid false interrupts and

should clear the flag bit, CCP4IF, following any such

change in operating mode.

16.2.4

CCP PRESCALER

There are four prescaler settings in Capture mode; they

are specified as part of the operating mode selected by

the mode select bits (CCP4M3:CCP4M0). Whenever

the CCP module is turned off or the CCP module is not

in Capture mode, the prescaler counter is cleared. This

means that any RESET will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

a non-zero prescaler. Example 16-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 16-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 16-2:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Note:

If the RG3/CCP4 is configured as an out-

put, a write to the port can cause a capture

condition.

CLRF

CCP4CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS

; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF

CCP4CON

; Load CCP1CON with

; this value

CCPR4H

CCPR4L

TMR1H

TMR1L

Set Flag bit CCP4IF

TMR3

Enable

Q’s

CCP1CON<3:0>

RG3/CCP4 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

TMR3H

TMR3L

TMR1

Enable

T3CCP2

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