IIS2DULPX datasheet(101/106 Pages) STMICROELECTRONICS

101 / 106 page

Table 54.

FREE_FALL register description ........................................................ 49

Table 55.

MD1_CFG register .................................................................. 50

Table 56.

MD1_CFG register description.......................................................... 50

Table 57.

MD2_CFG register .................................................................. 50

Table 58.

MD2_CFG register description.......................................................... 50

Table 59.

WAKE_UP_SRC register ............................................................. 51

Table 60.

WAKE_UP_SRC register description ..................................................... 51

Table 61.

TAP_SRC register .................................................................. 52

Table 62.

TAP_SRC register description .......................................................... 52

Table 63.

SIXD_SRC register ................................................................. 52

Table 64.

SIXD_SRC register description ......................................................... 52

Table 65.

ALL_INT_SRC register ............................................................... 53

Table 66.

ALL_INT_SRC register description....................................................... 53

Table 67.

STATUS register ................................................................... 53

Table 68.

STATUS register description ........................................................... 53

Table 69.

FIFO_STATUS1 register .............................................................. 54

Table 70.

FIFO_STATUS1 register description ...................................................... 54

Table 71.

FIFO_STATUS2 register .............................................................. 54

Table 72.

FIFO_STATUS2 register description ...................................................... 54

Table 73.

OUT_X_L register .................................................................. 54

Table 74.

OUT_X_L register description .......................................................... 54

Table 75.

OUT_X_H register .................................................................. 54

Table 76.

OUT_X_H register description .......................................................... 54

Table 77.

OUT_Y_L register .................................................................. 55

Table 78.

OUT_Y_L register description .......................................................... 55

Table 79.

OUT_Y_H register .................................................................. 55

Table 80.

OUT_Y_H register description .......................................................... 55

Table 81.

OUT_Z_L register .................................................................. 55

Table 82.

OUT_Z_L register description .......................................................... 55

Table 83.

OUT_Z_H register .................................................................. 55

Table 84.

OUT_Z_H register description .......................................................... 55

Table 85.

OUT_T_AH_QVAR_L register .......................................................... 56

Table 86.

OUT_T_AH_QVAR_L register description .................................................. 56

Table 87.

OUT_T_AH_QVAR_H register .......................................................... 56

Table 88.

OUT_T_AH_QVAR_H register description.................................................. 56

Table 89.

AH_QVAR_CFG register.............................................................. 56

Table 90.

AH_QVAR_CFG register description ..................................................... 56

Table 91.

SELF_TEST register ................................................................ 57

Table 92.

SELF_TEST register description ........................................................ 57

Table 93.

I3C_IF_CTRL register ............................................................... 57

Table 94.

I3C_IF_CTRL register description ....................................................... 57

Table 95.

EMB_FUNC_STATUS_MAINPAGE register ................................................ 57

Table 96.

EMB_FUNC_STATUS_MAINPAGE register description ........................................ 57

Table 97.

FSM_STATUS_MAINPAGE register ...................................................... 58

Table 98.

FSM_STATUS_MAINPAGE register description .............................................. 58

Table 99.

MLC_STATUS_MAINPAGE register ...................................................... 58

Table 100. MLC_STATUS_MAINPAGE register description .............................................. 58

Table 101. SLEEP register .................................................................... 58

Table 102. SLEEP register description ............................................................ 58

Table 103. EN_DEVICE_CONFIG register ......................................................... 59

Table 104. EN_DEVICE_CONFIG register description ................................................. 59

Table 105. FUNC_CFG_ACCESS register ......................................................... 59

Table 106. FUNC_CFG_ACCESS register description ................................................. 59

Table 107. FIFO_DATA_OUT_TAG register......................................................... 59

Table 108. FIFO_DATA_OUT_TAG register description ................................................ 59

IIS2DULPX

List of tables

DS14580 - Rev 1

page 101/106

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