IIS2DULPX datasheet(102/106 Pages) STMICROELECTRONICS

102 / 106 page

Table 109. Identification of sensor in FIFO ......................................................... 60

Table 110. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers .................................... 60

Table 111. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description ............................ 60

Table 112. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers .................................... 60

Table 113. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description ............................ 60

Table 114. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers .................................... 61

Table 115. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description............................. 61

Table 116. FIFO_BATCH_DEC register ........................................................... 61

Table 117. FIFO_BATCH_DEC register description ................................................... 61

Table 118. Accelerometer batch data rate .......................................................... 61

Table 119. TAP_CFG0 register ................................................................. 62

Table 120. TAP_CFG0 register description ......................................................... 62

Table 121. TAP_CFG1 register ................................................................. 62

Table 122. TAP_CFG1 register description ......................................................... 62

Table 123. TAP_CFG2 register ................................................................. 63

Table 124. TAP_CFG2 register description ......................................................... 63

Table 125. TAP_CFG3 register ................................................................. 63

Table 126. TAP_CFG3 register description ......................................................... 63

Table 127. TAP_CFG4 register ................................................................. 63

Table 128. TAP_CFG4 register description ......................................................... 63

Table 129. TAP_CFG5 register ................................................................. 64

Table 130. TAP_CFG5 register description ......................................................... 64

Table 131. TAP_CFG6 register ................................................................. 64

Table 132. TAP_CFG6 register description ......................................................... 64

Table 133. TIMESTAMP output registers .......................................................... 65

Table 134. TIMESTAMP output register description ................................................... 65

Table 135. Register address map - embedded functions ................................................ 66

Table 136. PAGE_SEL register ................................................................. 68

Table 137. PAGE_SEL register description ......................................................... 68

Table 138. EMB_FUNC_EN_A register............................................................ 68

Table 139. EMB_FUNC_EN_A register description ................................................... 68

Table 140. EMB_FUNC_EN_B register............................................................ 69

Table 141. EMB_FUNC_EN_B register description ................................................... 69

Table 142. EMB_FUNC_EXEC_STATUS register .................................................... 69

Table 143. EMB_FUNC_EXEC_STATUS register description ............................................ 69

Table 144. PAGE_ADDRESS register ............................................................ 69

Table 145. PAGE_ADDRESS register description .................................................... 69

Table 146. PAGE_VALUE register ............................................................... 70

Table 147. PAGE_VALUE register description ....................................................... 70

Table 148. EMB_FUNC_INT1 register ............................................................ 70

Table 149. EMB_FUNC_INT1 register description .................................................... 70

Table 150. FSM_INT1 register.................................................................. 71

Table 151. FSM_INT1 register description ......................................................... 71

Table 152. MLC_INT1 register.................................................................. 72

Table 153. MLC_INT1 register description ......................................................... 72

Table 154. EMB_FUNC_INT2 register ............................................................ 72

Table 155. EMB_FUNC_INT2 register description .................................................... 72

Table 156. FSM_INT2 register.................................................................. 73

Table 157. FSM_INT2 register description ......................................................... 73

Table 158. MLC_INT2 register.................................................................. 74

Table 159. MLC_INT2 register description ......................................................... 74

Table 160. EMB_FUNC_STATUS register.......................................................... 74

Table 161. EMB_FUNC_STATUS register description.................................................. 74

Table 162. FSM_STATUS register ............................................................... 75

Table 163. FSM_STATUS register description ....................................................... 75

IIS2DULPX

List of tables

DS14580 - Rev 1

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