AX88196BLF datasheet(3/86 Pages) ASIX

3 / 86 page

ASIX ELECTRONICS CORPORATION

AX88196BLF

FIGURES

FIG - 1 AX88196B BLOCK DIAGRAM.................................................................................................................................4

FIG - 2 AX88196B PIN OUT DIAGRAM...............................................................................................................................5

FIG - 3 INTERNAL SRAM MAP ..........................................................................................................................................12

FIG - 4 RECEIVE BUFFER RING..........................................................................................................................................16

FIG - 5 RECEIVE BUFFER RING AT INITIALIZATION...........................................................................................................17

FIG - 6 TX / RX FLOW CONTROL ......................................................................................................................................27

FIG - 7 EEPROM CONNECTIONS.......................................................................................................................................29

FIG - 8 PME AND IRQ SIGNAL GENERATION.....................................................................................................................30

FIG - 9 SMI CONNECTIONS................................................................................................................................................63

TABLES

TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP ........................................................................................................7

TAB - 2 10/100MBPS TWISTED-PAIR INTERFACES PINS GROUP ...........................................................................................7

TAB - 3 BUILT-IN PHY LED INDICATOR PINS GROUP .........................................................................................................7

TAB - 4 EEPROM BUS INTERFACE SIGNALS GROUP............................................................................................................7

TAB - 5 MISCELLANEOUS PINS GROUP .................................................................................................................................8

TAB - 6 MII PINS GROUP .....................................................................................................................................................9

TAB - 7 EEPROM DATA FORMAT EXAMPLE .....................................................................................................................10

TAB - 8 CSR ADDRESS MAPPING .....................................................................................................................................11

TAB - 9 LOCAL MEMORY MAPPING ..................................................................................................................................11

TAB - 10 INTERNAL SRAM MAP 00H ~ 1FH ...................................................................................................................11

TAB - 11 INTERNAL SRAM MAP 0400H ~ 040FH ...........................................................................................................11

TAB - 12 BYTE LANE MAPPING ........................................................................................................................................28

TAB - 13 POWER MANAGEMENT STATUSES ......................................................................................................................29

TAB - 14 PAGE 0 OF MAC CORE REGISTERS MAPPING ....................................................................................................32

TAB - 15 PAGE 1 OF MAC CORE REGISTERS MAPPING ....................................................................................................33

TAB - 16 PAGE 2 OF MAC CORE REGISTERS MAPPING ....................................................................................................34

TAB - 17 PAGE 3 OF MAC CORE REGISTERS MAPPING ....................................................................................................35

TAB - 18 THE EMBEDDED PHY REGISTERS ......................................................................................................................55

TAB - 19 SMI MANAGEMENT FRAME FORMAT.................................................................................................................63

TAB - 20 MII MANAGEMENT FRAMES- FIELD DESCRIPTION.............................................................................................63

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