AX88196BLF datasheet(6/86 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88196BLF

2.0 Signal Description

The following abbreviations are used in AX88196B pinout tables:

All pin names with the “n” suffix are low-active signals.

Input 1.8V

Output 1.8V

Input 3.3V with 5V tolerant

Output 3.3V with 5V tolerant

Tri-state with 5V tolerant

Bi-directional I/O, 3.3V with 5V tolerant

4mA driving strength

8mA driving strength

Schmitt trigger

Internal Pull Up 75Kohm

Internal Pull Down 75kohm

Power Pin

Analog

2.1 Local CPU Bus Interface Signals Group

Signal

Type

Pin No.

Description

SA[4:0]

74, 75, 76, 77, 79

System Address: Signals SA[4:0] are address bus input lines.

Used to select internal CSR’s.

SA[5] or

FIFO_SEL

I5/PD

System Address or FIFO Select: When driven high, all accesses

to the AX88196B are to the RX or TX data buffer FIFO (DP).

AX88196B supports two kinds of Data Port for

receiving/transmitting packets from/to AX88196B. One is the

PIO Data Port (offset 10h); the other one is the SRAM-like Data

Port (e.g. offset 800h ~ FFFh for Samsung2440 processor as

described in Appendix A4 of AX88196B datasheet). The

SRAM-like Data Port address range depends on which address

line of host processor is being connected to the address line

SA5/FIFO_SEL of AX88196B.

Software on host CPU can issue Single Data Read/Write

command to both PIO Data Port and SRAM-like Data Port.

However, to use Burst Data Read/Write commands, one has to

use SRAM-like Data Port, which requires SA5/FIFO_SEL (pin

45) of AX88196B connecting to an upper address line of host

CPU. Our reference schematic has SA5/FIFO_SEL pin

connected to upper address line for supporting Burst Data

Read/Write commands.

SD[15:0]

B5/8m

43, 44, 45, 46, 47, 48,

49, 50, 52, 53, 54, 55,

57, 58, 59, 60

System Data Bus: Signals SD[15:0] constitute the bi-directional

data bus.

IRQ

O5/T5/8m

Programmable Interrupt request. Programmable polarity, source

and buffer types.

Can be configure by EEPROM auto-loader or BTCR (offset 15h)

CSn

Chip Select: Active low.

RDn

Read: Active low strobe to indicate a read cycle.

WRn

Write: Active low strobe to indicate a write cycle. This signal also

used to wakeup the AX88196B when it is in reduced power state.

IOIS16n

T5/8m

16 Bit Port: For ISA bus used. The IOIS16n is asserted when the

address at the range corresponds to an I/O address to which the

chip responds, and the I/O port addressed is capable of 16-bit

access.

AEN or PSEN

Address Enable: When 186, ISA mode, this signal is active low

to access AX88196B.

PSEN: When 51 modes, this signal is active high to access

AX88196B.

AX88196BLF Datasheet(PDF) 6 Page - ASIX Electronics Corporation

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