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AX88196BLF Datasheet(PDF) 41 Page - ASIX Electronics Corporation |
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AX88196BLF Datasheet(HTML) 41 Page - ASIX Electronics Corporation |
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41 / 86 page ![]() ASIX ELECTRONICS CORPORATION 41 AX88196BLF 5.1.20 Transmit Configuration Register (TCR) Page0 Offset 0DH (Write) Field Name Description 7 FDU Full Duplex This bit configure MAC media mode is Full Duplex or not. 0: Half duplex (Default) 1: Full duplex This duplex setting was wire or with MCR bit-7. Each one goes high then configures MAC as full-duplex. AX88196B will ignore this bit and MCR bit-7 when using internal PHY. 6 PD Pad Disable 0: Pad will be added when packet length less than 60. (Default) 1: Pad will not be added when packet length less than 60. 5 RLO Retry of late collision 0: Don’t retransmit packet when late collision happens. (Default) 1: Retransmit packet when late collision happens. 4:3 - Reserved 2:1 LB1, LB0 Encoded Loop-back Control These encoded configuration bits set the type of loop-back that is to be performed. LB1 LB0 Mode0 0 0 Normal operation (Default) Mode 1 0 1 Internal AX88196B loop-back Mode 2 1 0 PHY loop-back No Define 1 1 Reserved 0 CRC Inhibit CRC 0: CRC appended by transmitter. (Default) 1: CRC inhibited by transmitter. 5.1.21 Frame Alignment Error Tally Register (CNTR0) Page0 Offset 0DH (Read) Field Name Description (Default = 00h) 7:0 CNTR0 This counter is incremented every time a packet is received with a Frame Alignment Error. The packet must have been recognized by the address recognition logic. The counter is cleared after the processor reads it. 5.1.22 Data Configuration Register (DCR) Page0 Offset 0EH (Write) Field Name Description 7:2 - Reserved 1 - Reserved 0 WTS Word Transfer Select (Data Port Only) 0: Selects Data Port with byte-wide transfers. (Default) 1: Selects Data Port with word-wide transfers. 5.1.23 CRC Error Tally Register (CNTR1) Page0 Offset 0EH (Read) Field Name Description (Default = 00h) 7:0 CNTR1 This counter is incremented every time a packet is received with a CRC error. The packet must first be recognized by the address recognition logic. The counter is cleared after the processor reads it. |
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