AX88196BLF datasheet(9/86 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88196BLF

2.6 MII pins group

Signal

Type

Pin No.

Description

TXCLK

I/PD

Transmit Clock: TXCLK is a continuous clock from PHY. It provides

the timing reference for the transfer of the TXEN and TXD[3:0]

signals from the MII port to the PHY.

TXEN

O5/8m

Transmit Enable: TXEN is transition synchronously with respect to the

rising edge of TXCLK. TXEN indicates that the port is presenting

nibbles on TXD [3:0] for transmission.

TXD[3:0]

O5/8m

68, 69, 70, 71 Transmit Data: TXD[3:0] is transition synchronously with respect to

the rising edge of TXCLK. For each TXCLK period in which TXEN is

asserted, TXD[3:0] are accepted for transmission by the PHY.

COL

I/PD

Collision: this signal is driven by PHY when collision is detected.

CRS

I/PD

Carrier Sense: Asynchronous signal CRS is asserted by the PHY when

either transmit or receive medium is non-idle.

RXCLK

I/PD

Receive Clock: RXCLK is a continuous clock that provides the timing

reference for the transfer of the RXDV and RXD[3:0] signals from the

PHY to the MII port.

RXDV

I/PD

Receive Data Valid: RXDV is driven by the PHY synchronously with

respect to RXCLK. Asserted high when valid data is present on RXD

[3:0].

RXD[3:0]

I/PD

29, 30, 31, 32 Receive Data: RXD[3:0] is driven by the PHY synchronously with

respect to RXCLK.

MDC

O5/8m

Station Management Data Clock: The timing reference for MDIO. All

data transfers on MDIO are synchronized to the rising edge of this

clock.

MDIO

B5/PU

Station Management Data Input/Output: Serial data input/output

transfers from/to the PHYs.

Tab - 6 MII pins group

AX88196BLF Datasheet(PDF) 9 Page - ASIX Electronics Corporation

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