ACLK

RD/WR

ANC/CTRL

ADDR

DATA

DATA

ADDR

ADDR

DATA

AD[7:0]

AD[9:8]

AD[9]

AD[8]

DRIVEN

AD[9]

AD[8]

AD[9:8]

DRIVEN

WRITE

WRITE

WRITE

LMH0030

www.ti.com

SNLS219G – JANUARY 2006 – REVISED APRIL 2013

Figure 3. Control Data Write Timing

ANCILLARY DATA FUNCTIONS

The LMH0030 can multiplex Ancillary Data into the serial component video data stream. The ancillary data

packet structure, formatting and control words are given in standard SMPTE 291M. The data may reside in

portions of the horizontal and vertical blanking intervals. The data can consist of different types of message

packets including audio data. The LMH0030 supports ancillary data in the HANC and VANC areas of standard

definition component video and in the chrominance channel (C’r/C’b) only for high-definition operation. As it

applies to embedded (multiplexed) audio data, this function follows the recommended practice for AES/EBU

default Level A data handling.

Figure 4 shows the sequence of clock, data and control signals for writing Ancillary Data to the port. In ancillary

data write mode, 10-bit ancillary data is written into the AD[9:0] port and subsequently into the ancillary data

FIFO. From the FIFO, the ancillary data can be inserted into the ancillary data areas in the serial video data

stream. Ancillary data may be written to the FIFO only when in the ancillary data mode. Ancillary data cannot be

read from the FIFO through the AD Port.

The process of loading ancillary data into the FIFO is done during the active video portion of the video line.

Occurrence of the active video line interval is indicated by the H-bit in the fourth word of the TRS sequence. The

H-bit is available on I/O Port bit-2.

The ancillary data write process begins by making the ANC/CTRL input high and the RD/WR input low. Next, the

data words are presented to the port in sequence as specified in SMPTE 291M beginning with the DID word.

Data presented to the port within the required setup and hold time parameters will be written into the FIFO on the

rising edge of ACLK. The user has the option of including a checksum in the ANC input data or of having the

LMH0030 calculate and append the checksum. The LMH0030 will append the Ancillary Data Flag to each packet

automatically before multiplexing with the video data.

The process of writing ancillary data to the FIFO is effectively a double-buffered write operation. Therefore, in

order to properly write the last word of the data packet, the CRC, whether supplied with the ANC data packet or

internally generated, to the FIFO, ACLK must be toggled two additional times after the last data word is clocked

into the port (or when the CRC is being generated internally and appended). In the case where multiple packets

are being loaded to the FIFO, the additional clocks are issued after the last word of the final packet is received

by the port.

Writing of ancillary data to the FIFO, packet handling and insertion into the video data stream are controlled by a

system of masking and control bits in the control registers. These and other ancillary data control functions such

as CHKSUM ATTACH IN are explained in detail later in this data sheet.

Copyright © 2006–2013, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Links: LMH0030