E4

A4

B4

D4

DAT1B

DAT2B

DAT3B

CMDB

CMDB

CLKB

DAT0B

VCCA

DAT0A

DAT1A

DAT2A

DAT3A

CMDA

CLKA

CLK-f

GND

GND

VCCB

DAT0B

DAT1B

DAT2B

DAT3B

CMDB

CLKB

VDDA

DAT0

DAT1

DAT2

DAT3

CMD

CLK

CLKin

GND

CD

VSS

A2

D1

E1

A1

B1

C1

D2

E2

C2

C3

VCCA

VCCB

Memory Stick

Controller

™

TXS0206

C3

0.1 µF

C4

0.1 µF

C1

0.1 µF

VCCB

U1A

U2

B3

C4

D3

Memory Stick™

Connector

CD

CD

B2

VCC

SCLK

DATA3 (see Note)

INS

DATA2 (see Note)

DATA0/SDIO (see Note)

DATA1 (see Note)

BS

VSS

1

DAT1B

2

DAT0B

3

DAT2B

4

CD

5

DAT3B

6

CLKB

7

8

9

10

22

TXS0206A

SCES833B – NOVEMBER 2011 – REVISED APRIL 2016

www.ti.com

Product Folder Links: TXS0206A

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Copyright © 2011–2016, Texas Instruments Incorporated

System Examples (continued)

Figure 9. Interfacing With Memory Stick™ Card

10 Power Supply Recommendations

The TXS0206A does not require power sequencing between VCCA and VCCB during power-up so the power-

supply rails can be ramped in any order.

The EN pin is referenced to VCCA and when configured to low, will place all outputs into a high-impedance state.

To ensure the high-impedance state of the outputs during power up or power down, the EN pin must be tied to

GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The

minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver

controlling the EN pin.

Finally, the EN pin may be shorted to VCCA if the application does not require use of the high-impedance state at

any time.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, TI recommends following common printed-circuit board layout guidelines.

•

Bypass capacitors should be used on power supplies.

•

Short trace lengths should be used to avoid excessive loading

•

PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than

the one shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the

source driver

•

With very heavy capacitive loads, the one-shot can time-out before the signal is driven fully to the positive rail,

so it is recommended that this lumped-load capacitance be considered and kept below 50 pF to avoid O.S.

retriggering, bus contention, output signal oscillations, or other adverse system-level affects.