SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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Structure (Sequencer/Vector/Macro/ScanBridge) Control Registers

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Count Generator

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Shifter (TDO_SM/TDI_SM/TMS_SM)

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Comparator

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Expected and Mask Registers

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Serial Scan Interface Controller (SSIC) and ScanBridge Controller

The clock divider unit divides the system clock SCK based on the programmable divisor set in the clock divider to

generate TCK_SM. The TCK_SM control unit gates TCK_SM if the TDO_SM buffer is empty.

The TAP Tracker unit tracks the target's TAP controller state. The TAP Tracker determines whether the target's

TAP controller is in SIR or SDR state, so that the necessary pad bits are inserted.

The shifter block contains two 32-bit shift registers for TDO_SM and TDI_SM respectively, and a 16-bit shift

register for TMS_SM.

The comparator unit compares the serial input on the TDI_SM pin with the expected data, bit by bit, if the

compare bit of the Macro Structure is set. If the compare/mask bit is set, then the comparator unit compares only

those bits that are unmasked.

Expected and Mask Registers contain the data fetched from the memory. This data is used by the comparator to

compare the TDI_SM input with the expected data.

The SSIC provides the timing and control signals to synchronize the operation of the various blocks in the SSI.

The ScanBridge Controller consists of the control logic to set up the ScanBridge hierarchy, if the ScanBridge

Support Initiate/Release bit is enabled, prior to scanning test vectors out of TDO_SM.

CLOCK DIVIDER AND TCK_SM CONTROL

The clock divider is a binary divider with only one bit of the clock divider register set to one at any given time.

The SCANSTA101 SSI ignores bits 0, and 8-15 of the clock divider register, so the supported divisors are 2, 4, 8,

16, 32, 64 and 128.

To generate a TCK_SM of frequency SCK/4, the clock divider register should be set to 4 (00000100). This will

enable the gate at the output of bit 2 of the counter to generate a clock of SCK divided by 4. If in LotF mode, the

TCK_SM enable from the SSIC will gate TCK_SM when the TDO_SM buffer is empty.

TAP TRACKER

The TAP Tracker consists of a 16-bit register to track the IEEE Standard 1149.1 TAP state machine. The register

is one-hot encoded (meaning that only one bit in the TAP tracker register, corresponding to the current TAP

state, is set at a time) and will continuously track the target's TAP Controller based on the TMS_SM sequence.

The TAP Tracker is used by the ScanBridge support controller to determine whether the target's TAP controller is

in SIR or SDR state so that it can insert an appropriate number of pre and post-shift pad bits.

The TAP Tracker will enter Test-Logic Reset state upon setting the TRST bit (bit 5) in the Setup register or by

issuing a sequence of five TMS_SM high bits.

SHIFTER

The Shifter block contains two 32-bit shift registers for TDO_SM and TDI_SM respectively, and one 16-bit shift

register for TMS_SM. The TMS_SM shifter block diagram is shown in Figure 3, the TDO_SM shifter block

diagram is shown in Figure 4, and the TDI_SM shifter block diagram is shown in Figure 5.

Before the start of a vector processing the TMS_SM shifter is loaded with the least significant 16 bits of the

macro structure. Based on the pre-shift TCK_SM count, the TMS_SM shifter will skip (7 - pre-shift count) least

significant bits. e.g., if the pre-shift count is 4, the least significant 3 bits of the TMS_SM shifter will not be used to

drive TMS_SM during pre-shift. Similarly, if the post-shift is less than 7 then, during post shift only the number of

bits equal to the post-shift count following the macro structure bit 8 will be used to drive TMS_SM.

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