SCANSTA101

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SNLS057J – MAY 2002 – REVISED APRIL 2013

Table 10. SCAN BRIDGE SUPPORT STRUCTURE

Bit(s)

Function

0x00 - 0x0F

Levels of Scan Bridge support to be inserted in the scan chain

0x10 - 0x17

Hierarchical Level 0 Scan Bridge Address

0x18 - 0x1F

Hierarchical Level 0 Scan Bridge LSP

0x20 - 0x27

Hierarchical Level 1 Scan Bridge Address

0x28 - 0x2F

Hierarchical Level 1 Scan Bridge LSP

..x.. - ..x..

Hierarchical Level Scan Bridge Address and LSP

0x7F0 - 0x7F7

Hierarchical Level 125 Scan Bridge Address

0x7F8 - 0x7FF

Hierarchical Level 125 Scan Bridge LSP

MODULE DESCRIPTIONS

Figure 1 shows a high level view of the SCANSTA101. The Parallel Processor Interface (PPI) and the Serial

Scan Interface (SSI) connect to each other through a dual-port memory. The PPI provides a parallel interface for

transferring data into and out of the dual-port memory, and for configuring, controlling and obtaining the status of

the device. The SSI, which resides on the other side of the dual-port memory, provides the parallel-to-serial and

serial-to-parallel conversion paths for providing test data and test control to support the STA Master and IEEE

1532 functions.

DUAL PORT MEMORY

The Dual Port Memory module is a 2048 x 32 bit dual-port memory which acts as the buffer between the PPI and

the SSI. There are seven regions of memory as viewed from the processor side. These regions, shown in

Table 3, are TDO_SM, TDI_SM, Expected, Mask, Vector, Header/Trailer, Macro. Sequencer, and ScanBridge

Support. Each has a pointer which resides in the PPI.

The memory is big endian oriented and is viewed as a single entity from the SSI side, and the SSI maintains a

pointer. The dual port memory module does not include any logic outside of its own macro function, so all the

timing and support logic is included in the PPI and SSI sections. There is no logic included in the SCANSTA101

design to utilize the "busy" indicators to keep the user from overwriting memory locations. The only area where

this could occur in memory would be the TDI_SM memory space since both the SSI and PPI can write to this

space, but the drivers should not allow PPI writes to this area during normal operations. The Texas Instruments

SCAN Ease software does not allow PPI writes to the TDI_SM memory.

PARALLEL PROCESSOR INTERFACE

The overall function of the PPI is to receive the parallel data from the processor; store the data in the appropriate

register or memory location; act on the data if the data are PPI control data; provide status data back to the

processor; and provide a read path for result data to the processor. The PPI consists of seven main blocks of

logic. These blocks are the Edge Detector (ED), Processor Interface Controller (PIC), the Memory/Register

Decoder (MRD), the Word/Long Word Converter (WLWC), the Control Generator (CG), the Status/Interrupt

Generator (SIG) and the Flag Generator (FG).

WORD/LONG WORD CONVERTER

The Word/Long Word Converter (WLWC) has four 16-bit capture registers: a least significant/most significant

(LS/MS) word read capture register pair; and a LS/MS word write capture register pair.

Each register within the write register pair has a separate enable to allow for the necessary control to accomplish

word to long word conversions when in the 16-bit mode. In 32-bit mode, these enables are driven

simultaneously. A mux is provided in front of the MS word write capture register to select between the 32-bit and

16-bit mode external bus.

Only one enable and a mux select is needed to control the read capture register pair to accomplish the long word

to word conversions when in the 16- bit mode. In the 32-bit mode, the mux selection doesn't change, so 32 bits

are always driven. A mux is on either side of the LS word read capture register. The mux at the register output

provides for selection between the 32-bit and 16-bit mode. The mux at the register input is for selection between

register space and memory space.

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