SCANSTA101SMSLASHNOPB datasheet(29/42 Pages) TI2

29 / 42 page

SCANSTA101

www.ti.com

SNLS057J – MAY 2002 – REVISED APRIL 2013

16/32 bit Mode

Selects 16-bit or 32-bit external interface mode

'1'

32-bit external interface mode (used in macro form only)

'0'

16-bit external interface mode

TDO_SM Ctrl<11:10>

TDO_SM Control bits

'00'

Hold previous value

'01'

Default TDO Value

'10'

Default TDO Value

'11'

High impedance

Sync Bit Length "x"

Sync Bit Length bits represents the number of sync bits to be used when the Sync Bit Support

Enable bit (17 in the Macro Structure) is set. The value "x" is the binary encoded numeric value.

Default TDO Value

The value in this register will be sent out on the TDO_SM pin when performing a BIST or a STATE

Macro.

'1'

Drive TDO_SM to one.

'0'

Drive TDO_SM to zero.

Debug Mode

Control bit to put SCANSTA101 in debug mode

'1'

Debug mode.

'0'

Normal mode.

ScanBridge Support Initiate/Release

ScanBridge support enable

'1'

Enable ScanBridge support

'0'

Disable ScanBridge support

TRST

Processor initiated ScanMaster test reset (on TRST0_SM and TRST1_SM_N). Bit is cleared by a

processor write.

'1'

Set TRST outputs low (active) and reset SSI logic.

'0'

Set TRST outputs high

Reset

Processor commanded synchronous reset to the serial scan logic for 2 clocks. This bit is self

clearing.

'1'

Reset the entire chip.

'0'

Release serial scan logic reset

Test Loop-Back<1:0>

Test loop-back mode bits

'00'

Normal operation

'01'

Loop-back TDO_SM to TDI_SM

'10'

Loop-back TMS_SM to TDI_SM

'11'

All Dot1 (1149.1) pins placed in SEU tolerant safe mode with: TMS_SM = 1, TCK_SM = 0,

TDO_SM = Z, TRST0_SM = 0

Table 22. Clock Divider Register (CLKDIV) ($05)

Bit(s)

Type

Field

Address Offset

Reset Value

Reset Source

15:8

Reserved

00h

7:1

Divisor

00h

SYS_RST

Reserved (hard coded) (1)

(1)

LSB of the Clock Divider register is hard coded to zero.

Divisor<7:1>

Clock divisor for the division of the SCK clock to the serial scan clock.

'0000000'

No serial scan clock generated.

'0000001'

Divide SCK by 2

'0000010'

Divide SCK by 4

'0000100'

Divide SCK by 8

'0001000'

Divide SCK by 16

'0010000'

Divide SCK by 32

'0100000'

Divide SCK by 64

'1000000'

Divide SCK by 128

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