SCANSTA101

SNLS057J – MAY 2002 – REVISED APRIL 2013

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(c) Decrement the vector repeat count and return to Step 3E if the Compare or Mask/ Compare is not

enabled.

12. If the Vector is being used return to the Idle state.

MODE REGISTER WRITE TO VECTOR/SEQUENCER START

Figure 8 shows the timing from the processor write to the start of vector processing. Figure 9 shows the timing

from the processor write to the start of sequencer processing. A processor write to the Start registers is indicated

by a "new data" pulse. On the same SCK rising edge when the "new data" is detected to be high, the Start or

Setup register contents will be updated with new data. So, the decoding of the enables takes place during the

next clock cycle to determine whether to process the sequencer or a vector. Therefore, one clock after the "new

data" is detected, the SSIC starts loading the pointer register on consecutive cycles with the appropriate

addresses to fetch the Sequencer, Vector and Macro Structures. Once the headers are decoded and Structure

Control Registers are set up, the SSIC loads the pointer register so that data from the TDO_SM memory area is

fetched and loaded into the TDO_SM shifter before being shifted out. However if there are any sync bits and/or

header bits and/or ScanBridge support is enabled, then the sync bits and/or header bits and/or ScanBridge pre-

PAD bits will be loaded into the TDO_SM shifter before processing the actual test vector. Once the actual test

vector is completely shifted out, again depending on the ScanBridge support and/or the use of trailers, post-PAD

bits and the trailer bits are loaded and shifted out through the TDO_SM shifter.

The count length will be decremented by one with each shift. After shifting out all the current shifter contents the

shifter will be loaded with new data before the falling edge of the next TCK_SM, if the count length is not

exhausted. In the case where data cannot be loaded from the memory before the next falling edge of TCK_SM,

the TCK_SM will be gated until the data is available.

Figure 8. Timing from Mode Register Write to Vector Start

Figure 9. Timing from Mode Register to Sequencer Start

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