SCANSTA101

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SNLS057J – MAY 2002 – REVISED APRIL 2013

The SCANSTA101 memory is organized in big endian format. A memory write is accomplished by two

consecutive writes to the same location. When embedded software loads the TDO_SM memory, the least

significant 16 bits are written first and then the most significant 16 bits. Therefore, when the Sequencer or a

Vector is initialized the SSIC can directly fetch and load the long word to the TDO_SM shifter without any

modification.

Figure 3. TMS_SM Shifter

Figure 4. TDO_SM Shifter

Figure 5. TDI_SM Shifter

Reading from TDI_SM memory is accomplished by two consecutive reads. When reading from the TDI_SM

memory, the first read will contain the least significant 16 bits and the second read the most significant 16 bits.

The TDI_SM shifter unit consists of two 32-bit shift registers as shown in Figure 5. The shift register on top in the

figure is the LFSR register. Before using the TDI_SM LFSR register, the LFSR Exponent and LFSR Seed

registers must be written with valid data. The LFSR Exponent register must be written with a 3-bit binary

encoded value that selects one of the five available polynomials. The value written to the LFSR Seed registers is

used to initialize the TDI_SM LFSR register to a predetermined state. Once the test vector has completely

scanned in, the final contents of the LFSR register are transferred to the LFSR Result registers.

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