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PIC16F18346-I/SS Datasheet(PDF) 89 Page - Microchip Technology |
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PIC16F18346-I/SS Datasheet(HTML) 89 Page - Microchip Technology |
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89 / 471 page ![]() 2016-2017 Microchip Technology Inc. Preliminary DS40001839B-page 89 PIC16(L)F18326/18346 7.5 Register Definitions: Oscillator Control REGISTER 7-1: OSCCON1: OSCILLATOR CONTROL REGISTER 1 U-0 R/W-f/f(1) R/W-f/f(1) R/W-f/f(1) R/W-q/q(4) R/W-q/q(4) R/W-q/q(4) R/W-q/q(4) —NOSC<2:0>(2,3) NDIV<3:0>(2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared f = determined by fuse setting q = Reset value is determined by hardware bit 7 Unimplemented: Read as ‘0’ bit 6-4 NOSC<2:0>: New Oscillator Source Request bits The setting requests a source oscillator and PLL combination per Table 7-1. POR value = RSTOSC (Register 5-2). bit 3-0 NDIV<3:0>: New Divider Selection Request bits The setting determines the new postscaler division ratio per Table 7-2. Note 1: The default value (f/f) is set equal to the RSTOSC Configuration bits. 2: If NOSC is written with a reserved value (Table 7-1), the HFINTOSC will be automatically selected as the clock source. 3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value. 4: When RSTOSC = 110 (HFINTOSC 1 MHz) the NDIV bits will default to '0010' upon Reset; for all other NOSC settings, the NVID bits will default to '0000' upon Reset. REGISTER 7-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1) R-q/q(1) — COSC<2:0> CDIV<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Reset value is determined by hardware bit 7 Unimplemented: Read as ‘0’ bit 6-4 COSC<2:0>: Current Oscillator Source Select bits (read-only) Indicates the current source oscillator and PLL combination per Table 7-1. bit 3-0 CDIV<3:0>: Current Divider Select bits (read-only) Indicates the current postscaler division ratio per Table 7-2. Note 1: The Reset value (q/q) will match the NOSC<2:0>/NDIV<3:0> bits. |
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