1

3

FB

1

Linear

Regulator

2M

2.2 uH

CBST

EN

AGND

Regulator IC

CSS

Internal Passives

VOUT

CINint

COUT

SYNC

EP/

PGND

Comp

CIN

RFBB

SS

VREF

VIN

350 kHz

PWM

RFBT

Filter

SH

LMZ22010

SNVS687H – MARCH 2011 – REVISED AUGUST 2015

www.ti.com

7 Detailed Description

7.1 Overview

The architecture used is an internally compensated emulated peak current mode control, based on a monolithic

synchronous SIMPLE SWITCHER core capable of supporting high load currents. The output voltage is

maintained through feedback compared with an internal 0.8-V reference. For emulated peak current-mode, the

valley current is sampled on the down-slope of the inductor current. This is used as the DC value of current to

start the next cycle.

The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a

narrow duty cycle. By sampling the inductor current at the end of the switching cycle and adding an external

ramp, the minimum on-time can be significantly reduced, without the need for blanking or filtering which is

normally required for peak current-mode control.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Synchronization Input

The PWM switching frequency can be synchronized to an external frequency source. The PWM switching will be

in phase with the external frequency source. If this feature is not used, connect this input either directly to

ground, or connect to ground through a resistor of 1.5 k

Ω or less. The allowed synchronization frequency range

is 314 kHz to 600 kHz. The typical input threshold is 1.4 V. Ideally, the input clock must overdrive the threshold

by a factor of 2, so direct drive from 3.3-V logic via a 1.5-k

Ω or less Thevenin source resistance is

recommended.

NOTE

Applying a sustained logic 1 corresponds to zero Hz PWM frequency and will cause the

module to stop switching.

14

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