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6.5.1

PLL2 Controller Device-Specific Information

6.5.2

PLL2 Controller Operating Modes

6.5.3

PLL2 Controller Input Clock Electrical Data/Timing

CLKIN

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

DSP device as possible. For the best performance, TI requires that all the PLL external components be on

a single side of the board without jumpers, switches, or components other than the ones shown. For

reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For

the input clock timing requirements, see Section 6.5.3, PLL2 Controller Input Clock Electrical Data/Timing.

As shown in Figure 6-7, the output of PLL2, PLLOUT, is directly fed to the DDR2 memory controller. This

clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUTz. Note that,

internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK1 of the PLL1

controller.

Note that there is a minimum and maximum operating frequency for PLLREF, and PLLOUT. The clock

generator must not be configured to exceed any of these constraints. For the PLL clocks input and output

frequency ranges, see Table 6-10.

Table 6-10. PLL2 Clock Frequency Ranges

CLOCK SIGNAL

REQUIRED FREQUENCY

UNIT

PLLREF (CLKIN2 )

26.6

MHz

PLLOUT (DDR2 clock)

533

MHz

Unlike the PLL1 controller that can operate in bypass and a PLL mode, the PLL2 controller only operates

in PLL mode. PLL2 isunlocked only during the power-up sequence (see Section 6.7) and is locked by the

time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

Table 6-11. Timing Requirements for CLKIN2(1)(2) (see Figure 6-8)

-720

-900

NO.

UNIT

PLL MODES x20

MIN

MAX

tc(CLKIN2)

Cycle time, CLKIN2

37.5

tw(CLKIN2H)

Pulse duration, CLKIN2 high

0.4C

tw(CLKIN2L)

Pulse duration, CLKIN2 low

0.4C

tt(CLKIN2)

Transition time, CLKIN2

1.2

tJ(CLKIN2)

Period jitter, (peak-to-peak) CLKIN2

100

(1)

The reference points for the rise and fall transitions are measured at 3.3-V VIL MAX and VIH MIN.

(2)

C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.

Figure 6-8. CLKIN2 Timing

Peripheral Information and Electrical Specifications

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