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TMS320DM647 Datasheet(PDF) 26 Page - Texas Instruments

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Part # TMS320DM647
Description  Digital Media Processor
PDF  167 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM647 Datasheet(HTML) 26 Page - Texas Instruments

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TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372A – MAY 2007 – REVISED JUNE 2007
Table 2-4. TERMINAL FUNCTIONS (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
OPER
DESCRIPTION
PULLUP/
VOLT
PULLDOWN
VP2CTL2/VSCRUN
Y1
I/O/Z
IPU
3.3 V
Video Port 2 Control 2 or VLYNQ serial clock run request (I/O)
VP2D02
W5
I/O/Z
IPD
3.3 V
Video Port 2 Data 2
VP2D03
AA2
I/O/Z
IPD
3.3 V
Video Port 2 Data 3
VP2D04
Y3
I/O/Z
IPD
3.3 V
Video Port 2 Data 4
VP2D05
U6
I/O/Z
IPD
3.3 V
Video Port 2 Data 5
VP2D06
Y2
I/O/Z
IPD
3.3 V
Video Port 2 Data 6
VP2D07
W3
I/O/Z
IPD
3.3 V
Video Port 2 Data 7
VP2D08
V5
I/O/Z
IPD
3.3 V
Video Port 2 Data 8
VP2D09
W4
I/O/Z
IPD
3.3 V
Video Port 2 Data 9
VP2D12/VRXD0
W2
I/O/Z
IPD
3.3 V
Video Port 2 Data 12 or VLYNQ receive data pin [0] (I)
VP2D13/VRXD1
V3
I/O/Z
IPD
3.3 V
Video Port 2 Data 13 or VLYNQ receive data pin [1] (I)
VP2D14/VRXD2
V4
I/O/Z
IPD
3.3 V
Video Port 2 Data 14 or VLYNQ receive data pin [2] (I)
VP2D15/VRXD3
U1
I/O/Z
IPD
3.3 V
Video Port 2 Data 15 or VLYNQ receive data pin [3] (I)
VP2D16/VTXD0
U3
I/O/Z
IPD
3.3 V
Video Port 2 Data 16 or VLYNQ transmit data pin [0] (O)
VP2D17/VTXD1
U2
I/O/Z
IPD
3.3 V
Video Port 2 Data 17 or VLYNQ transmit data pin [1] (O)
VP2D18/VTXD2
U5
I/O/Z
IPD
3.3 V
Video Port 2 Data 18 or VLYNQ transmit data pin [2] (O)
VP2D19/VTXD3
U4
I/O/Z
IPD
3.3 V
Video Port 2 Data 19 or VLYNQ transmit data pin [3] (O)
VIDEO PORT 3 OR EMIFA
VP3CLK0/AECLKIN
T1
I
IPD
3.3 V
Video Port 3 Clock 0 (I) or EMIFA external input clock (I)
VP3CLK1/AECLKOU
P1
I/O/Z
IPD
3.3 V
Video Port 3 Clock 1 or EMIFA output clock (O/Z)
T
VP3CTL0/ASDWE
T2
I/O/Z
IPU
3.3 V
Video Port 3 Control 0 or Asynchronous memory write
enable/Programmable synchronous interface write-enable
VP3CTL1/ARNW
R1
I/O/Z
IPU
3.3 V
Video Port 3 Control 1 or Asynchronous memory read/write (O/Z)
VP3CTL2/AOE
P2
I/O/Z
IPU
3.3 V
Video Port 3 Control 2 or Asynchronous/Programmable
synchronous memory output-enable (O/Z)
VP3D02/AED00
T6
I/O/Z
IPU
3.3 V
Video Port 3 Data 2 or EMIFA External Data 0
VP3D03/AED01
T5
I/O/Z
IPU
3.3 V
Video Port 3 Data 3 or EMIFA External Data 1
VP3D04/AED02
T4
I/O/Z
IPU
3.3 V
Video Port 3 Data 4 or EMIFA External Data 2
VP3D05/AED03
T3
I/O/Z
IPU
3.3 V
Video Port 3 Data 5 or EMIFA External Data 3
VP3D06/AED04
R6
I/O/Z
IPU
3.3 V
Video Port 3 Data 6 or EMIFA External Data 4
VP3D07/AED05
R5
I/O/Z
IPU
3.3 V
Video Port 3 Data 7 or EMIFA External Data 5
VP3D08/AED06
R4
I/O/Z
IPU
3.3 V
Video Port 3 Data 8 or EMIFA External Data 6
VP3D09/AED07
R3
I/O/Z
IPU
3.3 V
Video Port 3 Data 9 or EMIFA External Data 7
VP3D12/AED08
R2
I/O/Z
IPU
3.3 V
Video Port 3 Data 12 or EMIFA External Data 8
VP3D13/AED09
P6
I/O/Z
IPU
3.3 V
Video Port 3 Data 13 or EMIFA External Data 9
VP3D14/AED10
P5
I/O/Z
IPU
3.3 V
Video Port 3 Data 14 or EMIFA External Data 10
VP3D15/AED11
P4
I/O/Z
IPU
3.3 V
Video Port 3 Data 15 or EMIFA External Data 11
VP3D16/AED12
P3
I/O/Z
IPU
3.3 V
Video Port 3 Data 16 or EMIFA External Data 12
VP3D17/AED13
N4
I/O/Z
IPU
3.3 V
Video Port 3 Data 17 or EMIFA External Data 13
VP3D18/AED14
N6
I/O/Z
IPU
3.3 V
Video Port 3 Data 18 or EMIFA External Data 14
VP3D19/AED15
N5
I/O/Z
IPU
3.3 V
Video Port 3 Data 19 or EMIFA External Data 15
VIDEO PORT 4 OR EMIFA
VP4CLK0/AARDY
L1
I
IPU
3.3 V
Video Port 4 Clock 0 (I) or Asynchronous memory ready input (I)
VP4CLK1
K1
I/O/Z
IPD
3.3 V
Video Port 4 Clock 1
Device Overview
26
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