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TMS320DM647 Datasheet(PDF) 74 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 167 page  www.ti.com TMS320DM647/TMS320DM648 Digital Media Processor SPRS372A – MAY 2007 – REVISED JUNE 2007 Table 6-14. EDMA Channel Controller Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x02A0 1050 IER Interrupt Enable Register 0x02A0 1054 IERH Interrupt Enable Register High 0x02A0 1058 IECR Interrupt Enable Clear Register 0x02A0 105C IECRH Interrupt Enable Clear Register High 0x02A0 1060 IESR Interrupt Enable Set Register 0x02A0 1064 IESRH Interrupt Enable Set Register High 0x02A0 1068 IPR Interrupt Pending Register 0x02A0 106C IPRH Interrupt Pending Register High 0x02A0 1070 ICR Interrupt Clear Register 0x02A0 1074 ICRH Interrupt Clear Register High 0x02A0 1078 IEVAL Interrupt Evaluate Register 0x02A0 107C - Reserved 0x02A0 1080 QER QDMA Event Register 0x02A0 1084 QEER QDMA Event Enable Register 0x02A0 1088 QEECR QDMA Event Enable Clear Register 0x02A0 108C QEESR QDMA Event Enable Set Register 0x02A0 1090 QSER QDMA Secondary Event Register 0x02A0 1094 QSECR QDMA Secondary Event Clear Register 0x02A0 1098 - 0x02A0 1FFF - Reserved 0x02A0 2000- 0x02A0 2097 - Shadow Region 0 Channel Registers 0x02A0 2098 - 0x02A0 21FF - Reserved 0x02A0 2200 - 0x02A0 2297 - Shadow Region 1 Channel Registers 0x02A0 2298 - 0x02A0 23FF - Reserved 0x02A0 2400 - 0x02A0 2497 - Shadow Region 2 Channel Registers 0x02A0 2498 - 0x02A0 25FF - Reserved 0x02A0 2600 - 0x02A0 2697 - Shadow Region 3 Channel Registers 0x02A0 2698 - 0x02A0 27FF - Reserved 0x02A0 2800 - 0x02A0 2897 - Shadow Region 4 Channel Registers 0x02A0 2898 - 0x02A0 29FF - Reserved 0x02A0 2A00 - 0x02A0 2A97 - Shadow Region 5 Channel Registers 0x02A0 2A98 - 0x02A0 2BFF - Reserved 0x02A0 2C00 - 0x02A0 2C97 - Shadow Region 6 Channel Registers 0x02A0 2C98 - 0x02A0 2DFF - Reserved 0x02A0 2E00 - 0x02A0 2E97 - Shadow Region 7 Channel Registers 0x02A0 2E98 - 0x02A0 2FFF - Reserved Table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA events. Each of the parameter register sets consist of eight 32-bit word entries. Table 6-16 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. Peripheral Information and Electrical Specifications 74 Submit Documentation Feedback |
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