TMS320DM647 datasheet(97/167 Pages) TI

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AECLKIN

AECLKOUT1

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

Table 6-30. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the

EMIFA Module(1)(2)(3) (see Figure 6-14)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

tc(EKO)

Cycle time, AECLKOUT

E – 0.7

E + 0.7

tw(EKOH)

Pulse duration, AECLKOUT high

EH – 0.7

EH + 0.7

tw(EKOL)

Pulse duration, AECLKOUT low

EL – 0.7

EL + 0.7

tt(EKO)

Transition time, AECLKOUT

td(EKIH-EKOH)

Delay time, AECLKIN high to AECLKOUT high

td(EKIL-EKOL)

Delay time, AECLKIN low to AECLKOUT low

(1)

E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

(2)

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(3)

EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns

for EMIFA.

Figure 6-14. AECLKOUT Timing for the EMIFA Module

6.10.3.1 Asynchronous Memory Timing

Table 6-31. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)(2)(3)

(see Figure 6-15 and Figure 6-16)

-720

-900

NO.

UNIT

MIN

MAX

tsu(EDV-AOEH)

Setup time, AEDx valid before AAOE high

6.5

th(AOEH-EDV)

Hold time, AEDx valid after AAOE high

tsu(ARDY-EKOH)

Setup time, AARDY valid before AECLKOUT low

th(EKOH-ARDY)

Hold time, AARDY valid after AECLKOUT low

tw(ARDY)

Pulse width, AARDY assertion and deassertion

2E + 5

Delay time, from AARDY sampled deasserted on AECLKOUT falling to

td(ARDY-HOLD)

beginning of programmed hold period

Setup time, before end of programmed strobe period by which AARDY

tsu(ARDY-HOLD)

should be asserted in order to insert extended strobe wait states.

(1)

E = AECLKOUT period in ns for EMIFA

(2)

To specify data setup time, simply program the strobe width wide enough.

(3)

AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E

to specify setup and hold time is met.

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