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AECLKOUT

ACEx

ABE[7:0]

AEA[19:0]/

ABA[1:0]

AED[63:0]

AAOE/ASOE(A)

AR/W

AAWE/ASWE(A)

AARDY(B)

ByteEnables

Address

ReadData

Hold=1

Strobe=4

Setup=1

DEASSERTED

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

6.10.3.2 Programmable Synchronous Interface Timing

Table 6-33. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 6-18)

-720

-900

NO.

UNIT

MIN

MAX

tsu(EDV-EKOH)

Setup time, read AEDx valid before AECLKOUT high

th(EKOH-EDV)

Hold time, read AEDx valid after AECLKOUT high

1.5

Table 6-34. Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module(1) (see Figure 6-18–Figure 6-20)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

td(EKOH-CEV)

Delay time, AECLKOUT high to ACEx valid

1.3

4.9

td(EKOH-BEV)

Delay time, AECLKOUT high to ABEx valid

4.9

td(EKOH-BEIV)

Delay time, AECLKOUT high to ABEx invalid

1.3

td(EKOH-EAV)

Delay time, AECLKOUT high to AEAx valid

4.9

td(EKOH-EAIV)

Delay time, AECLKOUT high to AEAx invalid

1.3

td(EKOH-ADSV)

Delay time, AECLKOUT high to ASADS/ASRE valid

1.3

4.9

td(EKOH-OEV)

Delay time, AECLKOUT high to ASOE valid

1.3

4.9

td(EKOH-EDV)

Delay time, AECLKOUT high to AEDx valid

4.9

td(EKOH-EDIV)

Delay time, AECLKOUT high to AEDx invalid

1.3

td(EKOH-WEV)

Delay time, AECLKOUT high to ASWE valid

1.3

4.9

(1)

The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG):

•

Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency

•

Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

•

ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has

been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CE_EXT = 1).

•

Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with

deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (R_ENABLE = 1).

Figure 6-18. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)(A)

Peripheral Information and Electrical Specifications

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