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TMS320DM647 Datasheet(PDF) 73 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 167 page  www.ti.com TMS320DM647/TMS320DM648 Digital Media Processor SPRS372A – MAY 2007 – REVISED JUNE 2007 Table 6-14. EDMA Channel Controller Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x02A0 04C0 Q3E0 Event Queue 3 Entry Register 0 0x02A0 04C4 Q3E1 Event Queue 3 Entry Register 1 0x02A0 04C8 Q3E2 Event Queue 3 Entry Register 2 0x02A0 04CC Q3E3 Event Queue 3 Entry Register 3 0x02A0 04D0 Q3E4 Event Queue 3 Entry Register 4 0x02A0 04D4 Q3E5 Event Queue 3 Entry Register 5 0x02A0 04D8 Q3E6 Event Queue 3 Entry Register 6 0x02A0 04DC Q3E7 Event Queue 3 Entry Register 7 0x02A0 04E0 Q3E8 Event Queue 3 Entry Register 8 0x02A0 04E4 Q3E9 Event Queue 3 Entry Register 9 0x02A0 04E8 Q3E10 Event Queue 3 Entry Register 10 0x02A0 04EC Q3E11 Event Queue 3 Entry Register 11 0x02A0 04F0 Q3E12 Event Queue 3 Entry Register 12 0x02A0 04F4 Q3E13 Event Queue 3 Entry Register 13 0x02A0 04F8 Q3E14 Event Queue 3 Entry Register 14 0x02A0 04FC Q3E15 Event Queue 3 Entry Register 15 0x02A0 0500 - 0x02A0 051C - Reserved 0x02A0 0520 - 0x02A0 05FC - Reserved 0x02A0 0600 QSTAT0 Queue 0 Status Register 0x02A0 0604 QSTAT1 Queue 1 Status Register 0x02A0 0608 QSTAT2 Queue Status Register 2 0x02A0 060C QSTAT3 Queue Status Register 3 0x02A0 0610 - 0x02A0 061C - Reserved 0x02A0 0620 QWMTHRA Queue Watermark Threshold A Register for Q[3:0] 0x02A0 0624 – Reserved 0x02A0 0640 CCSTAT EDMA3CC Status Register 0x02A0 0644 - 0x02A0 06FC - Reserved 0x02A0 0700 - 0x02A0 0FFC - Reserved 0x02A0 1000 ER Event Register 0x02A0 1004 ERH Event Register High 0x02A0 1008 ECR Event Clear Register 0x02A0 100C ECRH Event Clear Register High 0x02A0 1010 ESR Event Set Register 0x02A0 1014 ESRH Event Set Register High 0x02A0 1018 CER Chained Event Register 0x02A0 101C CERH Chained Event Register High 0x02A0 1020 EER Event Enable Register 0x02A0 1024 EERH Event Enable Register High 0x02A0 1028 EECR Event Enable Clear Register 0x02A0 102C EECRH Event Enable Clear Register High 0x02A0 1030 EESR Event Enable Set Register 0x02A0 1034 EESRH Event Enable Set Register High 0x02A0 1038 SER Secondary Event Register 0x02A0 103C SERH Secondary Event Register High 0x02A0 1040 SECR Secondary Event Clear Register 0x02A0 1044 SECRH Secondary Event Clear Register High 0x02A0 1048 - 0x02A0 104C Reserved Submit Documentation Feedback Peripheral Information and Electrical Specifications 73 |
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