TMS320DM647 datasheet(24/167 Pages) TI

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TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

TYPE

INTERNAL

OPER

DESCRIPTION

PULLUP/

VOLT

PULLDOWN

SGMII0/1 and MDIO

SGMII0RXN

AA10

1.2 V

Differential SGMII port 0 RX input (negative)

SGMII0RXP

AA9

1.2 V

Differential SGMII port 0 RX input (positive)

SGMII0TXN

W11

1.2 V

Differential SGMII port 0 TX output (negative)

SGMII0TXP

Y11

1.2 V

Differential SGMII port 0 TX output (positive)

SGMII1RXN

AC9

1.2 V

Differential SGMII port 1 RX input (negative)

SGMII1RXP

AB9

1.2 V

Differential SGMII port 1 RX input (positive)

SGMII1TXN

1.2 V

Differential SGMII port 1 TX output (negative)

SGMII1TXP

1.2 V

Differential SGMII port 1 TX output (positive)

MDCLK

IPD

3.3 V

MDIO serial clock (MDCLK)

MDIO

I/O/Z

IPU

3.3 V

MDIO serial data (MDIO)

SPI or UART

SPICLK

F22

I/O/Z

IPU

3.3 V

SPI clock output

SPICS1/UARTTX

D23

I/O/Z

IPU

3.3 V

SPI chip select 1 or UART transmit (O/Z)

SPICS2/UARTRX

F23

I/O/Z

IPU

3.3 V

SPI chip select 2 or UART receive

SPIDI/UARTRTS

G23

I/O/Z

IPU

3.3 V

SPI data input or UART ready to send (O/Z)

SPIDO/UARTCTS

F21

I/O/Z

IPU

3.3 V

SPI data output or UART clear to send

TIMER 0/1 or GPIO[8:11]

T0INP12/GP08

E20

I/O/Z

IPD

3.3 V

Timer 0 input pin for lower 32-bit counter (I) or GPIO 8

T0OUT12/GP09

D21

I/O/Z

IPD

3.3 V

Timer 0 output pin for lower 32-bit counter (O/Z) or GPIO 9

T1INP12/GP10

E21

I/O/Z

IPD

3.3 V

Timer 1 input pin for lower 32-bit counter (I) or GPIO 10

T1OUT12/GP11

C22

I/O/Z

IPD

3.3 V

Timer 1 output pin for lower 32-bit counter(O/Z) or GPIO 11

MCASP OR VIDEO PORT OR VIC

AHCLKR

AC4

I/O/Z

IPD

3.3 V

McASP receive high-frequency master clock

AHCLKX

AC3

I/O/Z

IPD

3.3 V

McASP transmit high-frequency master clock

ACLKR

AC6

I/O/Z

IPD

3.3 V

McASP receive master clock

ACLKX

AC7

I/O/Z

IPD

3.3 V

McASP transmit master clock

AFSR

I/O/Z

IPD

3.3 V

McASP receive frame sync or left/right clock (LRCLK)

AFSX

AA7

I/O/Z

IPD

3.3 V

McASP transmit frame sync or left/right clock (LRCLK)

AXR0

AB6

I/O/Z

IPD

3.3 V

McASP data pin [0:7]

AXR1

IPD

3.3 V

AXR2

AA6

IPD

3.3 V

AXR3

AB4

IPD

3.3 V

AXR4

IPD

3.3 V

AXR5

IPD

3.3 V

AXR6

AA4

IPD

3.3 V

AXR7

IPD

3.3 V

STCLK/AXR8

I/O/Z

IPD

3.3 V

The STCLK signal drives the hardware counter for use by the

video ports (I) or McASP data pin 8.

VDAC/AXR9

AA5

I/O/Z

IPD

3.3 V

VCXO Interpolated Control Port (VIC) single-bit digital-to-analog

converter(VDAC) output (O) or McASP data pin 9

AMUTEIN

AB3

I/O/Z

IPD

3.3 V

McASP mute input

AMUTE

I/O/Z

IPD

3.3 V

McASP mute output (O/Z).

VIDEO PORT 0 OR GPIO[12:15]

VP0CLK0

Y23

IPU

3.3 V

Video Port 0 Clock 0 (I)

VP0CLK1

V23

I/O/Z

IPU

3.3 V

Video Port 0 Clock 1

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