LMH6586

SNCS105D – JULY 2008 – REVISED MARCH 2013

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Video and Sync Detection Enable Registers:

Registers 0x10 to 0x13 contain the video detection enable bits and registers 0x14 to 0x17 contain the sync

detection enable bits for all input channels. Any input (m) has both a video detection enable bit (VD_EN_m) and

a sync detection enable bit (SD_EN_m). When any enable bit is set low, the respective status bit will be excluded

from the OR-ing function used to set the FLAG output; otherwise, when the enable bit is set high, the respective

status bit will be included in the FLAG output function. Therefore, the FLAG will only logical-OR the status bits of

the channel(s) and type(s) of detection that are specifically enabled by the user as described in DETECTION

FLAG OUTPUT.

Video Detection Threshold Control Register

The video threshold voltage level is common to all 32 input channels and is selectable by programming VDT[2:0]

in register 0x1D. As shown in Table 1, the three LSBs (bits 2:0) of this register can be used to set the threshold

level in 95 mV steps (typical) above to the sync tip level of the DC-restored input. Refer to VIDEO DETECTION

for more information.

Input and Output Shutdown Registers

Each input channel and each output channel can be individually placed in shutdown (power save) mode to

reduce power consumption. Registers 0x18 to 0x1B contain the input shutdown bits (IN_PS_m) and registers

0x1E and 0x1F contain the output shutdown bits (OUT_PS_n), where “m” is any input channel and “n” is any

output channel. To place any input or output channel in shutdown mode, the respective bit should be set high;

otherwise, it should be set low for normal input or output operation. When in shutdown mode, the buffer (input or

output) will be placed in a high-impedance state.

Note: To put the entire device in power save mode, the PWDN input (pin 70) should be set high; otherwise, it

should be set low for normal operation.

Video Input Selection Registers

Registers 0x20 to 0x30 are used to control the routing of the crosspoint switch. Each output has a dedicated

input selection register, which can be programmed to select any input channel for routing to its respective output.

LMH6586 REGISTER MAP

Table 3. Video and Sync Detection Status Registers

Register

Address

R/W

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SYNC DETECT OUT

0x00h

R

SD_7

SD_6

SD_5

SD_4

SD_3

SD_2

SD_1

SD_0

(CH 0-7)

SYNC DETECT OUT

0x01h

R

SD_15

SD_14

SD_13

SD_12

SD_11

SD_10

SD_9

SD_8

(CH 8-15)

SYNC DETECT OUT

0x02h

R

SD_23

SD_22

SD_21

SD_20

SD_19

SD_18

SD_17

SD_16

(CH 16-23)

SYNC DETECT OUT

0x03h

R

SD_31

SD_30

SD_29

SD_28

SD_27

SD_26

SD_24

SD_24

(CH 24-31)

VIDEO DETECT OUT

0x04h

R

VD_7

VD_6

VD_5

VD_4

VD_3

VD_2

VD_1

VD_0

(CH 0-7)

VIDEO DETECT OUT

0x05h

R

VD_15

VD_14

VD_13

VD_12

VD_11

VD_10

VD_9

VD_8

(CH 8-15)

VIDEO DETECT OUT

0x06h

R

VD_23

VD_22

VD_21

VD_20

VD_19

VD_18

VD_17

VD_16

(CH 16-23)

VIDEO DETECT OUT

0x07h

R

VD_31

VD_30

VD_29

VD_28

VD_27

VD_26

VD_24

VD_24

(CH 24-31)

26

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