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L99PM72GXP Datasheet(PDF) 117 Page - STMicroelectronics

Part # L99PM72GXP
Description  Advanced power management system IC with embedded LIN and high speed CAN transceiver supporting CAN Partial Networking
PDF  129 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99PM72GXP Datasheet(HTML) 117 Page - STMicroelectronics

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L99PM72GXP
ST SPI
128
6.2.22
Global status register
The Global Error Flag is set once the watchdog failure counter (SR3<7:4>) is unequal to 0
(see also Section 2.5: Fail Safe Mode).
Table 132. Global status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Hex
value
Active high/low
High
High
Low
High
High
High
High
High
Default value in Normal Mode - after
correct WD trigger or after Read & Clear
on Error Flags
00100
000
20
Power ON
10000
000
80
Power ON weak battery (7)
10000
010
82
Communication error
11000
000
C0
VS overvoltage or undervoltage
10100
010
A2
WD failure
10100
001
A1
SPI Error (DI Stuck)
10100
001
A1
TSD1
10101
000
A8
TSD2
10111
001
B9
V1 Fail
10100
100
A4
Other Device Failure(8)
10100
000
A0
1.
The following Status Bits are reported in the Global Error Flag:
Global Status Register: Bits 6-0
Status Register 1: Bits 10-0
Status Register 3: Bits 15, 11, 7-2
2.
Communication Error: invalid number of CLOCK cycles during CSN low or failed parity check on standby command.
3.
Cleared with CLR command on SR3.
4.
Cleared with “READ and CLEAR” on SR3 (-> TSD1)
5.
Diagnosis bit only, VS Fail is not a Fail-Safe event; cleared by Read&Clear. Bit is automatically cleared at (VS >VSUV) and
(VS < VSOV) if Vlock_out_en = 0
6.
Cleared with a valid WD trigger (WD fail) or by clearing the corresponding status register related to failure. It is
recommended that the microcontroller does not enter standby mode, if a fail-safe event is indicated in the Global Status
Register. The selective wake-up configuration in CR 7 to 15 has to be re-written before sending the standby command.
7.
Slow VS ramp-up (VS undervoltage is filtered with 64µs after power-on reset)
8.
The Global Error Flag is raised due to a failure condition which is not reported in the Global Status Register. The Failure is
reported in the Status Registers 1-5



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