L99DZ80EP datasheet(45/68 Pages) STMICROELECTRONICS

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L99DZ80EP

Functional description of the SPI

4.1

General description

The SPI complies with Standard ST-SPI Interface Version 3.1.

Its communication is based on a Serial Peripheral Interface structure using CSN (Chip

Select Not), DI (Serial Data In), DO (Serial Data Out/Error) and CLK (Serial Clock) signal

lines.

4.1.1

Chip Select Not (CSN)

The CSN input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) is in high impedance state. A low signal wakes up the device and a serial

communication can be started. The state when CSN is going low until the rising edge of

CSN is called a communication frame.

4.1.2

Serial Data In (DI)

The DI input pin is used to transfer data serially into the device. The data applied to the DI is

sampled at the rising edge of the CLK signal. A stuck-at ‘0’ or ‘1’ enters the standby mode.

4.1.3

Serial Clock (CLK)

The CLK input signal provides the timing of the serial interface. The Data Input (DI) is

latched at the rising edge of Serial Clock CLK. The SPI can be driven by a micro controller

with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. Data on Serial

Data Out (DO) is shifted out at the falling edge of the serial clock (CLK). The serial clock

CLK must be active only during a frame (CSN low). Any other switching of CLK close to any

CSN edge could generate set up/hold violations in the SPI logic of the device. The clock

monitor counts the number of clock pulses during a communication frame (while CSN is

low). If the number of CLK pulses does not correspond to the frame width indicated in the

<SPI-frame-ID> (ROM address 03H) the frame is ignored and the <frame error> bit in the

<Global Status Byte> is set.

Note:

Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is

recommended.

4.1.4

Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and goes from high

impedance to a low or high level depending on the global status bit 7 (Global Error Flag).

The content of the selected status or control register is transferred into the data out shift

CLK shifts the next bit out.

4.1.5

SPI communication flow

At the beginning of each communication the master can read the contents of the

<SPIframe-ID> register (ROM address 03H) of the slave device.

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