UCC28056CDBVT datasheet(18/55 Pages) TI2

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D001

Line Voltage Rising

Line Voltage Falling

InMinPkL

InPkL

UCC28056

SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

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Feature Description (continued)

8.3.2 Line Voltage Feed-Forward

The controller applies Line Voltage Feed-Forward to the COMP pin voltage (VCO) before it computes the TON and

TDCM durations. This sequence ensures that COMP voltage represents input power regardless of Line voltage

and ensures that Burst operation occurs at the same level of output power for all Line voltages. It also ensures

fixed gain between the COMP pin voltage and input power simplifying compensation of the voltage control loop.

(11)

For ease of computation, UCC28056 employs seven discrete GFF levels, the most appropriate value being

selected by a series of comparators monitoring the peak input voltage level. Hysteresis is built into each

comparator to avoid repetitive changes in the selected GFF value and the step change in Line current that would

result. The comparator thresholds and GFF levels are selected to ensure that the demand to input power gain

(PIn/VCO) does not vary by more than ±20% over the full Universal Line voltage range (between 90 and 264

VRMS).

8.3.2.1 Peak Line Voltage Detection

UCC28056 internally reconstructs the input voltage waveform for the purpose of Peak Line voltage sensing and

Zero Current Detection (ZCD). In DCM or CrM mode the cycle average voltage across the Boost inductor must

be zero. UCC28056 generates an internal representation of input voltage by extracting the Drain waveform from

the ZCD/CS pin waveform and filtering it to extract the average Drain voltage across a switching cycle (VInSyn(θ))

The digital peak detector selects the value of GFF based upon the highest comparator threshold crossed over the

period THLinMax . The switch to a higher GFF value is implemented as soon as the corresponding threshold is

crossed. The switch to a lower GFF value is only implemented once the period THLinMax expires and the peak

detector has captured the Line voltage peak. The THLinMax timer is not synchronized to the Line operating

frequency.

Prior to the start of switching operation, at power - up or after a Burst - OFF period, the ZCD/CS pin voltage is

sampled and used to select the appropriate starting GFF level. This method assumes that the input rectifier and

capacitor after the rectifier bridge have captured the peak Line voltage during the period of no switching.

Figure 20. Normalized Gain vs Line Voltage

UCC28056CDBVT Datasheet(PDF) 18 Page - Texas Instruments

UCC28056CDBVT Datasheet(HTML) 18 Page - Texas Instruments

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