UCC28056CDBVT datasheet(37/55 Pages) TI2

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ZC2

ZC1

4.01nF

ZC1

10 pF

InRMSMax

ZCMax

ZC1

ZC2

14 mW

ZC1

ZC2

24.3 k

ZC1

3.24 M

9.72 M

ZCBoRise

ZC1

ZCBias

Err%

85V

12.0 M

100nA

UCC28056

www.ti.com

SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

Product Folder Links: UCC28056

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Equation 61 calculates the maximum value of RZC1 c, allowing a budget of 1% error due to input bias current

(IZCBias), on the lowest voltage threshold (VZCBoRise).

(61)

The upper resistor in the divider chain (RZC1) must withstand the peak output voltage under a surge test. For a

rugged solution, the resistor(s) in this location must have a voltage rating above the avalanche rating of the

Boost MOSFET. This design uses a series chain of three 1206, SMT, 3.24 M

Ω resistors for this location, which

yields DC voltage withstand capability above 600 V.

(62)

(63)

Use Equation 60 to calculate the power dissipation in the ZCD/CS pin divider resistors.

(64)

Once arranged on the PCB, the resistor divider circuit has some parasitic capacitance across both the upper

(RZC1) and lower (RZC2) resistors. Experience suggests a parasitic capacitance (CZC1) of approximately 0.1 pF

across resistor RZC1, when it is made up of three 1206 SMT components, assuming a compact PCB layout. In

theory this parasitic capacitance could be used to form the entire value of CZC1 and an appropriate value of CZC2

added to achieve the ratio required by Equation 56. In practice most designers choose to add an explicit

capacitor in this location to improve tolerance to small changes in layout, such as may occur when connecting

oscilloscope probes. Ensure the time constant for the divider does not extend over many switching cycles. This

limitation ensures that Line surge or system ESD transient events may disturb the ZCD/CS pin DC level but does

not persist over an excessive number of switching cycles.

Select a single 10-pF, 1000-V, 0805 SMT capacitor with 5% tolerance.

(65)

Use Equation 66 calculate the lower divider capacitor value.

(66)

In practice, once the final PCB layout is complete, adjust the lower capacitor value to account for parasitic

capacitances present on the PCB. Consider both the Drain and ZCD/CS pin waveforms and adjust the lower

capacitance value (CZC2) until the value allows the required ratio in signal amplitude. Use a low capacitance

probe for the ZCD/CS pin connection. Figure 28, Figure 29 and Figure 30 present the type of waveforms that

occur during this tuning process.

UCC28056CDBVT Datasheet(PDF) 37 Page - Texas Instruments

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