UCC28056CDBVT datasheet(19/55 Pages) TI2

19 / 55 page

TZCDR

First Valley Ipk Err

VDS(t)

IL(t)

DRV

TZCDR

First Valley Ipk Err

VIn

TON

UCC28056

www.ti.com

SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

Product Folder Links: UCC28056

Submit Documentation Feedback

Feature Description (continued)

8.3.3 Valley Switching and CrM/DCM Hysteresis

The UCC28056 controller achieves maximum efficiency enabling power switching operation when the drain

voltage of the MOSFET is at a minimum (sometimes referred to as valley), of the resonance that occurs during

the TDCM period . Any energy stored in the Drain node capacitance (CDE ) dissipates in the power switch during

its turnon transition time. Valley switching ensures minimum energy is stored in CDE prior to the turnon period

and hence minimum switching loss. After the TDCM period, the controller waits for the next available valley on the

drain voltage before initiating a new switching cycle. The actual TDCM duration is therefore always an integer

multiple of the drain resonance period. If the calculated TDCM period extends over a valley boundary the actual

TDCM duration steps up in value by one resonant period. This step change in TDCM duration causes a step

change in Line current that rapidly decays as the TON(θ) computation iterates to a new solution to reflect the step

change in TDCM duration. Line current distortion, resulting from valley transitions, is kept to a minimum by

computing the TDCM duration from the COMP voltage. The COMP voltage varies little over the period of a Line

cycle and hence the calculated TDCM duration changes very little over the period of a Line cycle.

Line current distortion is particularly severe during the transition from the first valley (CrM) to the second valley

(DCM) operation while the input voltage is low. In this region, the first valley duration is extended by the clamping

action of the power switch body diode. In this region Line current is reduced when switching on the first valley,

(CrM) , because the inductor current is negative at the start of the on period. The reduction in Line current is not

observed for second or subsequent valley (DCM) operation because the inductor current starts the on period

from zero. UCC28056 implements hysteresis in the TDCM computation to virtually eliminate the possibility of

repeated CrM/DCM transitions across a Line cycle. Such transitions can only occur if the twice Line frequency

ripple on the COMP voltage is greater than 12% at the CrM/DCM boundary.

Figure 21. Drain Voltage and Inductor Current Transitioning from DCM to CrM

8.3.3.1 Valley Delay Adjustment

The UCC28056 delivers maximum efficiency when controlling power stages that have widely differing natural

resonant frequencies. The application achieves this efficiency because the designer externally programs the

delay between the ZcdVIn comparator crossing and the rising edge of DRV (TZCDR). Ideal valley switching for

different power stage designs that may have very different natural resonant frequencies.

The TZCDR delay can be set to one of eight different values (TZCDR0 – TZCDR7) by setting the value of a resistor

(RDG) connected externally between the DRV and GND pins. During the startup period or when recovering from a

long fault, the controller transitions from the Stopb state to the RDGRdb state and then to the BstOffb state.

While in the RDGRdb state, an internal current source (IDG) transitions to the DRV pin. The the voltage that

results from this current determines the appropriate TZCDR delay. The controller uses this delay period for all

valley switching operation until a long fault causes the controller to return to the Stopb state.

UCC28056CDBVT Datasheet(PDF) 19 Page - Texas Instruments

UCC28056CDBVT Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL