UCC28056CDBVT datasheet(36/55 Pages) TI2

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InRMSMax

ZCMax

ZC1

ZC2

OutOvp2

Ovp2Th

451 V

InRMSBoRise

ZCBoRise

85.1 V

ZC1

ZC2

401

ZC1

ZC2

ZC1

ZC2

ZC1

ZC2

ZC1

ZC2

UCC28056

SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

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In theory, a simple resistor divider can be used to attenuate the Drain voltage waveform fed into the ZCD/CS pin.

In practice, the parasitic capacitance associated with the PCB traces and the ZCD/CS pin filter the attenuated

signal and introduce phase shift. The resulting distortion and phase shift negatively impact the ability of the part

to synchronize to the zero inductor current transitions. The problem is compounded by the need to limit power

dissipation in the resistive divider, which dictates the use of high resistance values, and increased filtering of the

attenuated signal.

Add a capacitor divider in parallel with the resistor divider in order to use of high value resistors without

introducing filtering and associated phase shift. In this case, ensure that the reactive divider ratio is equal to the

resistor divider ratio.

(55)

Hence:

(56)

There are number of internal voltage thresholds driven by the attenuated Drain voltage signal supplied to the

ZCD/CS pin. These include Brown-Out (VZCBoRise), Line feed-forward (VFFxRise, VFFxFall) and second output over-

voltage (VOvp2Th). The same external divider ratio (KZC) drives all of these thresholds. Scope to vary the

attenuation ratio specified is limited because it impacts all of these thresholds in unison.

(57)

(58)

The controller infers Line voltage from the switching cycle average voltage on the Drain node. Neglecting any

resistive voltage drop in the Boost inductor this must be equal to the voltage supplied from the input rectifier,

provided the Boost inductor current returns to zero at the end of each cycle (TM/CrM/DCM). Voltage drops in the

input rectifier bridge and EMI filter stage cause an error between predicted and measured threshold values. An

internal peak detector determines the peak input voltage across a Line half-cycle. Equation 58 above converts

this peak value to an RMS quantity, but assumes an ideal sinusoidal Line supply

Equation 59 calculates the output voltage required to trigger the second output overvoltage comparator (Ovp2).

(59)

This parameter is observed via the Drain waveform, voltage drops in the Boost Diode and series NTC resistor,

causes the Ovp2 comparator to trip at a lower output voltage level.

Power dissipation in the Drain sensing resistor divider chain reaches its highest value during the Burst OFF

condition. During the Burst OFF condition, the Drain voltage approximates a DC voltage equal to the Line voltage

peak. This approximation assumes the time constant CIN × (RZC1+ RZC2) is long compared with a Line half-

period. Under no-load conditions, the Burst OFF duty cycle is high therefore maximum power dissipation in the

Drain sensing resistor divider chain, occurs at high Line and no-load, as described in Equation 60.

(60)

UCC28056CDBVT Datasheet(PDF) 36 Page - Texas Instruments

UCC28056CDBVT Datasheet(HTML) 36 Page - Texas Instruments

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