UCC28056CDBVT datasheet(40/55 Pages) TI2

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u S u

Ctrl0

Ctrl

Z u

OSRe g

CO1

Ctrl

Out

Out Re g

CO1

Out

OutMax

Plant

Plant0

COMax

Out Re g

Out

Out Re g

OSDiv

OS11

OS12

OS2

15.5 mW

OS11

OS12

OS2

Out Re g

OSRe g

OS2

390 V

OS12

36.5 k

/ / 120 k

28.0 k

OS2

75 k

/ / 390 k

62.9 k

OS11

OS12

OS2

62.89 k

UCC28056

SLUSD37E – OCTOBER 2017 – REVISED NOVEMBER 2019

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Product Folder Links: UCC28056

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(78)

These two divider resistor values can be implemented using easily obtainable values as follows:

(79)

(80)

Actual regulation set point is therefore:

(81)

Power dissipated in the VOSNS resistor divider is:

(82)

9.2.2.5 Voltage Loop Compensation

The design of the voltage control loop of a PFC stage is requires compromise. The voltage control loop must be

fast to achieve a good transient response to steps in load current, but tTo minimize distortion of the Line current

it must be slow. This section describes the selection of compensation components that deliver a target Line

current distortion and phase margin.

9.2.2.5.1

Plant Model

The first step is to produce a small signal model of the PFC Boost converter. A constant power load is assumed

to be connected across the output capacitor. This provides the most accurate representation of a switched mode

regulator delivering constant output voltage. The plant gain is assumed to be independent of Line voltage due to

the action of the internal Line voltage feed-forward circuit. Across the Universal Line voltage range (90 VRMS-264

VRMS), plant gain actually varies by ±-20% due to the quantized nature of the Line voltage feed-forward circuit.

(83)

9.2.2.5.2

Compensator Design

The integrator response of the plant provides a gain roll off of –20dB/decade and introduces a phase lag of 90°.

A simple integrating compensation network provides unacceptable phase margin because it introduces a second

90° of phase lag into the voltage loop. To ensure adequate phase margin, use a type 2 compensation network to

provide the desired phase boost a the gain cross-over frequency. Equation 84 describes the mall-signal gain of

the error amplifier and type 2 compensation network.

(84)

Equation (84) may also be expressed as follows:

where

(86)

UCC28056CDBVT Datasheet(PDF) 40 Page - Texas Instruments

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