LAN8818DSLASHKDX datasheet(49/101 Pages) MICROCHIP

49 / 101 page

LAN8818D

DS00005832C-page 49

If the PTP Disable (PTP_DISABLE) bit is set, any frame modifications in process are completed, however no modifica-

tions are made to subsequent frames. Once all sub-modules are idle, the PTP Enable (PTP_ENABLE) and PTP Disable

(PTP_DISABLE) bits are cleared.

When the PTP Enable (PTP_ENABLE) bit goes low, the 1588 Local Time Counter is halted, no packet detection is per-

formed, no GPIO timestamping is performed, no GPIO event indication is done and no frame modifications are per-

formed. Ingress and egress frames are passed without any pipeline delays. Register writes are still allowed and any

5.9.9

1588 TIMING

For 1588 timing information, refer to the following Section 6.6, "AC Specifications" sub-sections:

• 1588 GPIO Timing

• 1588_REF_CLK Reference Clock Timing

• 1588_LD_ADJ Timing

• 1588 1PPS Format and Timing

• 1588 Serial Timestamp Interface (STI) Format and Timing

• 1588_EVENT_B Timing

• GPIO PTP Capture Timing

• RCVRD_CLK_OUT1/2 Timing

5.10

Energy Efficient Ethernet (EEE)

The device implements Energy Efficient Ethernet (EEE) as described in IEEE Standard 802.3az. The specification is

defined around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that support

the special signaling associated with EEE. EEE saves power by keeping the AC signal on the copper Ethernet cable at

approximately 0V peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up

status. This is referred to as Low Power Idle (LPI) mode or state.

As set by the MODE_SEL[4:0] configuration straps, the device has the EEE function enabled or disabled as the power-

up default setting. The EEE function can be enabled or disabled by setting or clearing the following EEE advertisement

bits in the EEE Advertisement register (MDIO Manageable Device (MMD) Address 7h, register 3Ch), followed by restart-

ing auto-negotiation (writing a ‘1’ to the Basic Control register, bit[9]):

• 1000BASE-T EEE (bit[2]) = ‘0/1’

// Disable/Enable 1000 Mbps EEE mode

• 100BASE-TX EEE (bit[1]) = ‘0/1’

// Disable/Enable 100 Mbps EEE mode

During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation

immediately, without blockage of traffic or loss of packet. This involves exiting LPI mode and returning to normal 100/

1000 Mbps operating mode. Wake-up times are <16 µs for 1000BASE-T and <30 µs for 100BASE-TX. The LPI state is

controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for:

• Transmit cable path only

• Receive cable path only

• Both transmit and receive cable paths

APPLICATION NOTE: 1588 packet processing requires TSU_ENABLE to be set for each applicable port and

PTP_ENABLE to be set for the chip. Individual port TSU functions may be initially

configured by assuring PTP_ENABLE is cleared (TSU_ENABLE can be either set of

cleared in this case). Individual port TSU functions may also be configured while other

1588 functions are running by assuring the applicable port TSU_ENABLE is cleared

(PTP_ENABLE is typically already set in this case).

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