MSC8103SLASHD datasheet(40/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

1-36

Freescale Semiconductor

Signals/Connections

1.7 JTAG Test Access Port Signals

The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test

Access Port and Boundary-Scan Architecture specification and described in Table 1-11.

1.8 Reserved Signals

Table 1-11.

JTAG Test Access Port Signals

Signal Name

Type

Signal Description

TCK

Input

Test Clock

A test clock signal for synchronizing JTAG test logic.

TDI

Input

Test Data Input

A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and

has an internal pull-up resistor.

TDO

Output

Test Data Output

A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively

driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK.

TMS

Input

Test Mode Select

Sequences the test controller’s state machine, is sampled on the rising edge of TCK, and has an

internal pull-up resistor.

TRST

Input

Test Reset

Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted

after power up.

Table 1-12.

Reserved Signals

Signal Name

Type

Signal Description

TEST

Input

Test

Used for manufacturing testing. You must connect this input to GND.

THERM[1–2]

—

Leave disconnected.

SPARE1, 5

—

Spare Pins

Leave disconnected for backward compatibility with future revisions of this device.

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