MSC8103SLASHD datasheet(15/104 Pages) FREESCALE

15 / 104 page

System Bus, HDI16, and Interrupt Signals

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

1-11

IRQ1

DP1

EXT_BG2

Input

Input/Output

Output

Interrupt Request 11

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 11

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity one pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 1 and D[8–15].

External Bus Grant 21,2

The MSC8103 asserts this pin to grant bus ownership to an external bus master.

IRQ2

DP2

EXT_DBG2

Input

Input/Output

Output

Interrupt Request 21

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 21

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity two pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 2 and D[16–23].

External Data Bus Grant 21,2

The MSC8103 asserts this pin to grant data bus ownership to an external bus master.

IRQ3

DP3

EXT_BR3

Input

Input/Output

Input

Interrupt Request 31

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 31

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity three pin should give odd parity (odd number of ones) on the group of signals that includes

data parity 3 and D[24–31].

External Bus Request 31,2

An external master asserts this pin to request bus ownership from the internal arbiter.

IRQ4

DP4

DREQ3

EXT_BG3

Input

Input/Output

Input

Output

Interrupt Request 41

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 41

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity four pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 4 and D[32–39].

DMA Request 31

An external peripheral uses this pin to request DMA service.

External Bus Grant 31,2

The MSC8103 asserts this pin to grant bus ownership to an external bus master.

Table 1-5.

System Bus, HDI16, and Interrupt Signals (Continued)

Signal

Data Flow

Description

MSC8103/D Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

MSC8103/D Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL