MSC8103SLASHD datasheet(63/104 Pages) FREESCALE

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AC Timings

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-23

2.6.7

CPM Timings

Table 2-20.

CPM Input Characteristics

No.

Characteristic

Typical

Unit

FCC input set-up time before low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input)

FCC input hold time after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input)

SCC/SMC/SPI/I2C input set-up time before low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input)

SCC/SMC/SPI/I2C input hold time after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial clock input)

TDM input set-up time before low-to-high serial clock transition

TDM input hold time after low-to-high serial transition

PIO/TIMER/DMA input set-up time before low-to-high serial clock transition

PIO/TIMER/DMA input hold time after low-to-high serial clock transition

Note:

FCC, SCC, SMC, SPI, I2C are non-multiplexed serial interface signals.

Table 2-21.

CPM Output Characteristics

No.

Characteristic

Min

Max

Unit

FCC output delay after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial input clock)

SCC/SMC/SPI/I2C output delay after low-to-high clock transition

a. internal clock (BRGxO)

b. external clock (serial input clock)

TDM output delay after low-to-high serial clock transition

PIO/TIMER/DMA output delay after low-to-high serial clock transition

Note:

FCC, SCC, SMC, SPI, I2C are Non-Multiplexed Serial Interface signals.

Figure 2-18.

FCC Internal Clock Diagram

BRGxO

FCC inputs

FCC outputs

29a

17a

41a

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