MSC8103SLASHD datasheet(55/104 Pages) FREESCALE

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AC Timings

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-15

Table 2-16.

AC Timing for SIU Inputs

No.

Characteristic

Value2

Units

Hold time for all signals after the 50% level of the DLLIN rising edge

0.5

11a

ABB/AACK set-up time before the 50% level of the DLLIN rising edge

3.5

11b

DBG/DBB/BR/TC set-up time before the 50% level of the DLLIN rising edge

5.0

11c

ARTRY set-up time before the 50% level of the DLLIN rising edge

4.0

11d

TA set-up time before the 50% level of the DLLIN rising edge

•

Pipeline mode

•

Non-pipeline mode

3.5

4.0

11e

TEA set-up time before the 50% level of the DLLIN rising edge

•

Pipeline mode

•

Non-pipeline mode

4.0

3.0

11f

PSDVAL set-up time before the 50% level of the DLLIN rising edge

•

Pipeline mode

•

Non-pipeline mode

3.5

11g

TS set-up time before the 50% level of the DLLIN rising edge

5.0

11h

BG set-up time before the 50% level of the DLLIN rising edge

4.5

Data bus set-up time before the 50% level of the DLLIN rising edge in Normal

•

Pipeline mode

•

Non-pipeline mode

2.5

5.0

Data bus set-up time before the 50% level of the DLLIN rising edge in ECC and PARITY modes

•

Pipeline mode

•

Non-pipeline mode

2.5

8.0

DP set-up time before the 50% level of the DLLIN rising edge

•

Pipeline mode

•

Non-pipeline mode

4.0

9.0

15a

Address bus set-up time before the 50% level of the DLLIN rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

•

Non-extra cycle mode (SIUBCR[EXDD] = 1)

5.0

8.0

15b

Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the DLLIN rising edge

•

Extra cycle mode (SIUBCR[EXDD] = 0)

•

Non-extra cycle mode (SIUBCR[EXDD] = 1)

5.0

5.5

161

PUPMWAIT/IRQ signals set-up time before the 50% level of the DLLIN rising edge

3.0

Notes:

The set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation.

Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are

measured at the pin.

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