R5F5671CDDLE datasheet(131/179 Pages) RENESAS

131 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 131 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

Note 1. tPAcyc: PCLKA cycle

Figure 2.58

Simple SPI Clock Timing

Table 2.41

Simple SPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-speed interface high-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

2—

tPAcyc

Figure 2.58

SCK clock cycle input (slave)

—

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise/fall time

Output

tSPCKr, tSPCKf

—5

Input

—

µs

Data input setup time

Master

tSU

0.5

—

Figure 2.59 to

Figure 2.62

Slave

2.5

—

Data input hold time

Master

—

Slave

2.5

—

Data output delay time

Master

tOD

—4

Slave

—

Data output hold time

Master

tOH

0—

Slave

—

Data rise/fall time

Output

tDr, tDf

—5

Input

—

Slave access time

tSA

—5

tPAcyc

Figure 2.61,

Figure 2.62

Slave output release time

tREL

—5

tPAcyc

SS input setup time

tLEAD

1—

tSPcyc

Figure 2.59 to

Figure 2.62

SS input hold time

tLAG

1—

tSPcyc

SS input rise/fall time

tSSLr, tSSLf

—1

µs

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

(n = 010, 011)

SCKn output

(master)

SCKn input

(slave)

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