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R5F5671CDDLE Datasheet(PDF) 136 Page - Renesas Technology Corp

Part # R5F5671CDDLE
Description  Renesas MCUs
PDF  179 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F5671CDDLE Datasheet(HTML) 136 Page - Renesas Technology Corp

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R01DS0373EJ0120 Rev.1.20
Page 136 of 179
Sep 30, 2024
RX671 Group
2. Electrical Characteristics
2.4.7.12
RSPI
Note 1. tPAcyc: PCLKA cycle
Note 2. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in
combination with the pins in the same group. All RSPI AC timings are measured in combination with the pins in the same group.
Table 2.43
RSPI Timing
Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,
VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,
PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the drive capacity control register.
Item
Symbol
Min.*1
Max.*1
Unit*1
Test
Conditions*2
RSPI
RSPCK clock cycle
Master
tSPcyc
2—
tPAcyc Figure 2.68
Slave
4
—
RSPCK clock high pulse
width
Master
tSPCKWH
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—ns
Slave
0.4
0.6
tSPcyc
RSPCK clock low pulse
width
Master
tSPCKWL
(tSPcyc – tSPCKr
– tSPCKf) / 2 – 3
—ns
Slave
0.4
0.6
tSPcyc
RSPCK clock rise/fall time
Output
tSPCKr,
tSPCKf
—5
ns
Input
—
1
µs
Data input setup time
Master
tSU
6
—
ns
Figure 2.69 to
Figure 2.74
Slave
8.3
—
Data input hold time
Master PCLKA divi-
sion ratio set to
1/2
tHF
0—
ns
PCLKA divi-
sion ratio set to
a value other
than 1/2
tH
tPAcyc
—ns
Slave
8.3
—
SSL setup time
Master
tLEAD
18
tSPcyc
Slave
4
—
tPAcyc
SSL hold time
Master
tLAG
18
tSPcyc
Slave
4
—
tPAcyc
Data output delay time
Master
tOD
—6.3
ns
Slave
—
28
Data output hold time
Master
tOH
0—
ns
Slave
0
—
Successive transmission
delay time
Master
tTD
tSPcyc + 2 × tPAcyc
8 × tSPcyc
+ 2 × tPAcyc
ns
Slave
4 × tPAcyc
—
MOSI and MISO
rise/fall time
Output
tDr, tDf
—5
ns
Input
—
1
µs
SSL rise/fall time
Output
tSSLr,
tSSLf
—5
ns
Input
—
1
µs
Slave access time
tSA
—
28
ns
Figure 2.73,
Figure 2.74
Slave output release time
tREL
—28
ns



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