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PSD833F2 Datasheet(PDF) 86 Page - STMicroelectronics |
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PSD833F2 Datasheet(HTML) 86 Page - STMicroelectronics |
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86 / 110 page  PSD835G2 PSD8XX Family 85 -70 -90 Symbol Parameter Conditions Min Max Min Max Unit tISCCF TCK Clock Frequency (except for PLD) (Note 1) 20 18 MHz tISCCH TCK Clock High Time (Note 1) 23 26 ns tISCCL TCK Clock Low Time (Note 1) 23 26 ns tISCCF-P TCK Clock Frequency (for PLD only) (Note 2) 2 2 MHz tISCCH-P TCK Clock High Time(for PLD only) (Note 2) 240 240 ns tISCCL-P TCK Clock Low Time(for PLD only) (Note 2) 240 240 ns tISCPSU ISC Port Set Up Time 6 8 ns tISCPH ISC Port Hold Up Time 5 5 ns tISCPCO ISC Port Clock to Output 21 23 ns tISCPZV ISC Port High-Impedance to Valid Output 21 23 ns tISCPVZ ISC Port Valid Output to High-Impedance 21 23 ns ISC Timing (5 V ± 10%) Microcontroller Interface – PSD835G2 AC/DC Parameters (5V ± 10% Versions) Symbol Parameter Min Typ Max Unit Flash Program 8.5 sec Flash Bulk Erase (Preprogrammed to 00) (Note 1) 3 30 sec Flash Bulk Erase 10 sec tWHQV3 Sector Erase (Preprogrammed to 00) 1 30 sec tWHQV2 Sector Erase 2.2 sec tWHQV1 Word Program 14 1200 µs Program/Erase Cycles (Per Sector) 100,000 cycles tWHWLO Sector Erase Time-Out 100 µs tQ7VQV DQ7 Valid to Output Valid (Data Polling) (Note 2) 30 ns Flash Program, Write and Erase Times (5 V ± 10%) NOTE: 1. Programmed to all zeros before erase. 2. The polling status DQ7 is valid tQ7VQV ns before the data DQ0-7 is valid for reading. NOTES: 1. For “non-PLD” programming, erase or in ISC by-pass mode. 2. For program or erase PLD only. |
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