PSD833F2 datasheet(15/110 Pages) STMICROELECTRONICS

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PSD8XX Family

PSD835G2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

****

JTAG_Enable

JTAG Enable Register

Bit definitions:

JTAG_Enable

1 = JTAG Port is Enabled.

0 = JTAG Port is Disabled.

8.0

Definition

(cont.)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Pgr7

Pgr6

Pgr5

Pgr4

Pgr3

Pgr2

Pgr1

Pgr0

Page Register

Bit definitions:

Configure Page input to PLD. Default Pgr[7:0] = 00.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLD

APD

Mcells clk

array-clk

Turbo

enable

PMMR0 Register

Bit definitions: (default is 0)

Bit 1 0 = Automatic Power Down (APD) is disabled.

1 = Automatic Power Down (APD) is enabled.

Bit 3 0 = PLD Turbo is on.

1 = PLD Turbo is off, saving power.

Bit 4 0 = CLKIN input to the PLD AND array is connected.

Every CLKIN change will power up the ZPLD when Turbo bit is off.

1 = CLKIN input to PLD AND array is disconnected, saving power.

Bit 5 0 = CLKIN input to the PLD Micro

⇔Cells is connected.

1 = CLKIN input to the PLD Micro

⇔Cells is disconnected, saving power.

*Not used bit should be set to zero.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLD

array WRh

array Ale

array Cntl2 array Cntl1 array Cntl0

PMMR1 Register

Bit definitions (default is 0):

Bit 0 0 = Address A[7:0] are connected into the PLD array.

1 = Address A[7:0] are blocked from the PLD array, saving power.

Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4.

Bit 2 0 = Cntl0 input to the PLD AND array is connected.

1 = Cntl0 input to the PLD AND array is disconnected, saving power.

Bit 3 0 = Cntl1 input to the PLD AND array is connected.

1 = Cntl1 input to the PLD AND array is disconnected, saving power.

Bit 4 0 = Cntl2 input to the PLD AND array is connected.

1 = Cntl2 input to the PLD AND array is disconnected, saving power.

Bit 5 0 = Ale input to the PLD AND array is connected.

1 = Ale input to the PLD AND array is disconnected, saving power.

Bit 6 0 = WRh/DBE input to the PLD AND array is connected.

1 = WRh/DBE input to the PLD AND array is disconnected, saving power.

*Not used bit should be set to zero.

PSD833F2 Datasheet(PDF) 15 Page - STMicroelectronics

PSD833F2 Datasheet(HTML) 15 Page - STMicroelectronics

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