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PSD833F2 Datasheet(PDF) 13 Page - STMicroelectronics

Part # PSD833F2
Description  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD833F2 Datasheet(HTML) 13 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7
Port Pin 6
Port Pin 5
Port Pin 4
Port Pin 3
Port Pin 2
Port Pin 1
Port Pin 0
Data In Registers – Port A, B, C, D, E, F and G
8.0
Register Bit
Definition
All the registers in the PSD835G2 are included here for reference. Detail description of the
registers are found in the Functional Block section of the Data Sheet.
Bit definitions:
Read only registers, read Port pin status when Port is in MCU I/O input Mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7
Port Pin 6
Port Pin 5
Port Pin 4
Port Pin 3
Port Pin 2
Port Pin 1
Port Pin 0
Data Out Registers – Port A, B, C, D, E, F and G
Bit definitions:
Latched data for output to Port pin when pin is configured in MCU I/O output mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7
Port Pin 6
Port Pin 5
Port Pin 4
Port Pin 3
Port Pin 2
Port Pin 1
Port Pin 0
Direction Registers – Port A, B, C, D, E, F and G
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin in Input mode (default).
Set Register Bit to 1 = configure corresponding Port pin in Output mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7
Port Pin 6
Port Pin 5
Port Pin 4
Port Pin 3
Port Pin 2
Port Pin 1
Port Pin 0
Control Registers – Ports E, F and G
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin in MCU I/O mode (default).
Set Register Bit to 1 = configure corresponding Port pin in Latched Address Out mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7
Port Pin 6
Port Pin 5
Port Pin 4
Port Pin 3
Port Pin 2
Port Pin 1
Port Pin 0
Drive Registers – Ports A, B, D, E, and G
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin in CMOS output driver (default).
Set Register Bit to 1 = configure corresponding Port pin in Open Drain output driver.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7
Port Pin 6
Port Pin 5
Port Pin 4
Port Pin 3
Port Pin 2
Port Pin 1
Port Pin 0
Drive Registers – Ports C and F
Bit definitions:
Set Register Bit to 0 = configure corresponding Port pin as CMOS output driver (default).
Set Register Bit to 1 = configure corresponding Port pin in Slew Rate mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port Pin 7
Port Pin 6
Port Pin 5
Port Pin 4
Port Pin 3
Port Pin 2
Port Pin 1
Port Pin 0
Enable Out Registers – Ports A, B, C and F
Bit definitions: Read Only Registers
Register Bit <j> = 0 indicates Port pin driver is in tri-state mode (default).
Register Bit <j> = 1 indicates Port pin driver is enabled.



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