PSD833F2 datasheet(10/110 Pages) STMICROELECTRONICS

10 / 110 page

PSD835G2

PSD8XX Family

Pin*

(TQFP

Pin Name Pkg.)

Type

Description

PA0-PA7

51-58

I/O

Port A, PA0-7. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port

Drain

2. CPLD Micro

⇔Cell (MCell A0-7) output.

3. Latched, transparent or registered PLD input.

PB0-PB7

61-68

I/O

Port B, PB0-7. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. CPLD Micro

⇔Cell (MCell B0-7) output.

3. Latched, transparent or registered PLD input.

PC0-PC7 41-48

I/O

Port C, PC0-7. This port is pin configurable and has multiple

CMOS

functions:

or Slew

1. MCU I/O — standard output or input port.

Rate

2. External chip select (ECS0-7) output.

3. Latched, transparent or registered PLD input.

PD0

I/O

Port D pin PD0 can be configured as:

CMOS

1. ALE or AS input — latches addresses on ADIO0-15 pins

or Open

2. AS input — latches addresses on ADIO0-15 pins on the

Drain

rising edge.

3. Input to the PLD.

4. Transparent PLD input.

PD1

I/O

Port D pin PD1 can be configured as:

CMOS

1. MCU I/O

or Open

2. Input to the PLD.

Drain

3. CLKIN clock input — clock input to the CPLD

Micro

⇔Cells, the APD power down counter and CPLD

AND Array.

PD2

I/O

Port D pin PD2 can be configured as:

CMOS

1. MCU I/O

or Open

2. Input to the PLD.

Drain

3. CSI input — chip select input. When low, the CSI enables

the internal PSD memories and I/O. When high, the

internal memories are disabled to conserve power. CSI

trailing edge can get the part out of power-down mode.

PD3

I/O

Port D pin PD3 can be configured as:

CMOS

1. MCU I/O

or Open

2. Input to the PLD.

Drain

PE0

I/O

Port E, PE0. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. TMS input for JTAG/ISP interface.

PE1

I/O

Port E, PE1. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. TCK input for JTAG/ISP interface (Schmidt Trigger).

PE2

I/O

Port E, PE2. This port is pin configurable and has multiple

CMOS

functions:

or Open

1. MCU I/O — standard output or input port.

Drain

2. Latched address output.

3. TDI input for JTAG/ISP interface.

Table 5.

PSD835G2

Descriptions

(cont.)

PSD833F2 Datasheet(PDF) 10 Page - STMicroelectronics

PSD833F2 Datasheet(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL