NRF52820-QDAA-R datasheet(40/437 Pages) NORDIC

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Core components

• Avoid situations where more than one bus master is accessing the same slave.

• If more than one bus master is accessing the same slave, make sure that the bus bandwidth is not

exhausted.

Below is a list of bus masters in the system and their priorities.

Bus master name

Description

CPU

CTRL-AP

USB

SPIM1/SPIS1/TWIM1/TWIS1

Same priority and mutually exclusive

RADIO

CCM/ECB/AAR

Same priority and mutually exclusive

UARTE0

SPIM0/SPIS0/TWIM0/TWIS0

Same priority and mutually exclusive

Table 12: AHB bus masters (listed from highest to lowest priority)

Defined bus masters are the CPU and peripherals with implemented EasyDMA. The available slaves are

RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix is

illustrated in Memory on page 15.

4.8 Debug

Debug system offers a flexible and powerful mechanism for non-intrusive debugging.

DAP

CPU

ARM Cortex-M4

SWDCLK

SWDIO

SW-DP

POWER

CxxxPWRUPREQ

CxxxPWRUPRACK

Power

External

debugger

Peripherals

RAM & flash

APB/AHB

AHB

AHB-AP

DAP bus

interconnect

APPROTECT.PALL

CTRL-AP

UICR

NVMC

Figure 7: Debug overview

The main features of the debug system are the following:

• Two-pin serial wire debug (SWD) interface

• Flash patch and breakpoint (FPB) unit that supports:

• Two literal comparators

• Six instruction comparators

4.8.1 DAP - Debug access port

An external debugger can access the device via the DAP.

4463_156 v1.0

NRF52820-QDAA-R Datasheet(PDF) 40 Page - Nordic Semiconductor

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